Looking for a PLL design flow using Cadence

[cmosbjt]

PLL design in Cadence ?

Hi,

Can anyone tell me the PLL design flow using Cadence? (freq is about 10MHz) Do you only use transient simulation? I think I will start with the system simulation using behavior model (VHDL or Verilog), then replace the ideal block with real circuit. But will it take too long to simulate? What is the practical way to design PLL in Cadence?

Thanks

 

[Chethan]

Re: PLL design in Cadence ?

Hi,

Can anyone tell me the PLL design flow using Cadence? (freq is about 10MHz) Do you only use transient simulation? I think I will start with the system simulation using behavior model (VHDL or Verilog), then replace the ideal block with real circuit. But will it take too long to simulate? What is the practical way to design PLL in Cadence?

Thanks

Not only time domain analysis like transient but U will have to do frequency domain analysis also on ur circuits for a PLL. SpectreRF can help u do frequency domain simulation.

 

[floatice]

PLL design in Cadence ?

pll system simulation you can use some special tools,such as the tool in BEST's book.

 

[khouly]

Re: PLL design in Cadence ?

cadence spectreRF have many RF simulation engins like PSS periodic stedy state and others , these can be used in PLL simulation

@DS has also some simulations engines can be used like circuit envelop simulation which is hybird time domain frequncy domian simulation used in simulation for modulation and demodulation

ELDORF of ment0r also have SST , and MODSST simulation based on harmonic balance technology ver useful in simlation of VCO and PLL circuits

finally HSPICE RF also can be used

but most of designs must be simulated with tarnsient simulation

and donot forget to get a good machine to run ur PLL designs , i have seen some simulations take about 3 to 4 days "it was a PLL"


wish this help

khouly

 

[shankar]

Re: PLL design in Cadence ?

hi
if you are borrowing an architecture and change your transistors to the need of your specs then you could first freeze the specs i.e. convert the system level specs into the circuit level specs from the models and the libraries you have for your design. This is for simulation.
i dont think there is a big deal in what i have said. if the architecture works then your circuit should. it all depends on how well you size your mosfets to meet specs.
now you need to decide for what your PLL is going to be used for. i.e clock synthesis, FM demod( this will be in RF or IF and hence will need the use of fabrication inductors) else you could do with just current starving delay cell ring oscillators for the VCO.
then you could go to the layout.

 

[jcpu]

Re: PLL design in Cadence ?

HELLO

For 10MHz (fixed frequency) PLL, we only need

(1) system calculation: like matlab / NS PLL tools / circuit sage ...
making sure loop bandwidth, charge pump current, tuning sensitivity,
are lined-up all right.

(2) Gate level implementation of PLL blocks, by HSPICE ...accordingly.
A few issues to watch out:
*** temperature + process corners can change loop parameters
so much that design cycle usually repeat from (1) again.
PLL are not very forgiving with respect to loop parameter changes...
*** be very aware of PSRR + noise from VCC or GND,
hence P&R is always critical.

(3) can afford only one typical post-sim ....they often takes a few days.

Good luck,

 

[mircea]

Re: PLL design in Cadence ?

you should do most of the analises in spectre RF, if you want to be sure of your pll:
pss, pnoise, sp, qpnoise (is faster than pnoise) + all standard: dc, ac

 

[darkk]

PLL design in Cadence ?

For simulation on sys level (you have to do that, I thingk.) , you can go to some tool other than the Cadence's. Can't remember exactly, but you can google it with the keyword like "MIT pll tool" to get to the right place.

 

[mostafa zean]

Re: PLL design in Cadence ?

system
then verify your specs on it
after that make the schematic model for each block
and run the system with one block (schematic)+the others(veriloga) if ok put another block(schematic)instead of the first block and so on until check all system well

Added after 2 minutes:

make a veriloga model for ech block in the system
then verify your specs on it
after that make the schematic model for each block
and run the system with one block (schematic)+the others(veriloga) if ok put another block(schematic)instead of the first block and so on until check all system well

 

[bluestatic]

PLL design in Cadence ?

pll design is a good case to practice mix flow like AMS of cadence, you might want to model you feedback divider with verilog-A to save the simulation time

 

[jcpu]

Re: PLL design in Cadence ?

mircea siad

you should do most of the analises in spectre RF, if you want to be sure of your pll:
pss, pnoise, sp, qpnoise (is faster than pnoise) + all standard: dc, ac

looks very interesting;
could someone please provide some reference material.
thanks in advance,