cmosbjt
Full Member level 5

PLL design in Cadence ?
Hi,
Can anyone tell me the PLL design flow using Cadence? (freq is about 10MHz) Do you only use transient simulation? I think I will start with the system simulation using behavior model (VHDL or Verilog), then replace the ideal block with real circuit. But will it take too long to simulate? What is the practical way to design PLL in Cadence?
Thanks
Hi,
Can anyone tell me the PLL design flow using Cadence? (freq is about 10MHz) Do you only use transient simulation? I think I will start with the system simulation using behavior model (VHDL or Verilog), then replace the ideal block with real circuit. But will it take too long to simulate? What is the practical way to design PLL in Cadence?
Thanks