Hi
Anyone know about any free Vera tool available. The only vera tool i have seen is the one given by synopsys. There is no trial version of that tool.
Similarly is there any free tool for System Verilog?
Unfortunately tools supporting both the verifications languages
viz. vera and system verilog are not free! But if you are studing
in some school ur school may get this tools from Synopsys for
free or with nominal fee's!