Looking for a core for implementing a serial ATA controller

[guybrush]

SERIAL ATA

Hi everybody.
I'm locking for a core for implementing a serial ata controller in FPGA.
Someone can help me?

 

[eltonjohn]

Re: SERIAL ATA

i don't know if you can get those streaming speeds ( 3.12 Gigabits/s) with a reagular FPGA .. Look at the xilinx website maybe now they have an app on how to configure the RocketIO for Serial ATA .. it was suppossed to be possible .. with the Virtex IIpro .In any case it will be possible with the new Virtex-4

 

[guybrush]

Re: SERIAL ATA

Maybe it's possible to find some IC that performs the serialisation and deserialisation, so that the FPGA can go with a more easy to handle low frequency. On Intel site i find a specification of such a IC that i report here:

SATA PHY Interface Specification (SAPIS), Draft Rev 0.90
SAPIS (SATA PHY Interface Specification) is intended to enable the development of functionally equivalent SATA PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a SAPIS compliant PHY, and it defines a standard interface between such a PHY and a link layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell; The SAPIS specification is defined to allow various approaches to be used. Where possible the SAPIS specification references the SATA specification rather than repeating its content. SAPIS requires PHY's to support Gen 1 signaling, support of Gen 2 is optional

I don't know if there is a chip with such a function!

 

[lucbra]

Re: SERIAL ATA

Any embedded SerDes has the possibility to achieve the drive strength required for Serial ATA. The speed is usual not the issue.
Even V4 has not the possibility.
As suggested above, go for a dedicated solution. These chips are so unexpensive, that it isn't worth the effort.

Regards