Long transistor layout dummy positioning

[Vitor Przedzmirski]

Hello guys, I hope you can help my with this question:

Considering a very simple current mirror circuit, with A diode-connected and B mirroring its current.

A and B have multiplier = 2 and their W/L is 1um/10um.

I would like to know which of the following configurations you like the most, considering the position of the dummy transistors, and why =D





From my knowledge, I would go for the second one. I always saw layouts (considering transistors with W > L) where the dummy is abutted/next to drain or source, so it "protects" the diffusion, which does not happen in the first option.

However, I also saw in layout reference books and some presentations that in this same configuration, the dummies should be added like in the first picture...

What can you tell me about this? The other option is just put dummies all around, but there is the area trade-off and other considerations...

I appreciate if you could help me.

(this same discussion applies to cross-coupled layouts!!! )

Thank you! :-D

 

[Ata_sa16]

I have not used the second one ever. I would do like this.



if you use dummies all around you layout will be so complicated and large with lots of parasitics.

 

[dick_freebird]

I would say that the S/D contact structure will stand off
the dummies so far that they may be of little help in the
L direction. Furthermore the L being large lessens the
impact of etch variation, which is the main interest. If
the FETs are narrow, however, then you are exposed to
more variation in the W direction and parallel (perhaps
min W as you seem to show) guards may be useful. A
long wide square-aspect device, I might be inclined to
forget about dummies altogether if space was tight and
matching not an extreme concern (and if you're that
concerned, might want to look at correction methods
that take out what's left).

 

[Vitor Przedzmirski]

I would say that the S/D contact structure will stand off
the dummies so far that they may be of little help in the
L direction. Furthermore the L being large lessens the
impact of etch variation, which is the main interest. If
the FETs are narrow, however, then you are exposed to
more variation in the W direction and parallel (perhaps
min W as you seem to show) guards may be useful. A
long wide square-aspect device, I might be inclined to
forget about dummies altogether if space was tight and
matching not an extreme concern (and if you're that
concerned, might want to look at correction methods
that take out what's left).

Thanks for your answer!

So, if I understood you right, do you agree that the second layout option is more appropriate? I'm sorry if I couldn't get the ideia.

In any case, I agree with you that it really depends on the matching needs and transistor aspect, but I still think that's a little bit confusing to choose the right dummies with W/L ratio < 1...