Elnegm
Member level 1
I'm using FPGA Xilix virtex 2 pro FG45 and Xilinx ISE
The problem that ISE when i Synthesis my verilog core which is 8051 it continue Synthesis,it Synthesis for along time and didn't fiinsh,the module that ISE still Synthesis and didn't fininsh is the ROM,so i can't Synthesis the core ,Any solutions?
Thanks in advance
The problem that ISE when i Synthesis my verilog core which is 8051 it continue Synthesis,it Synthesis for along time and didn't fiinsh,the module that ISE still Synthesis and didn't fininsh is the ROM,so i can't Synthesis the core ,Any solutions?
Thanks in advance