samuel_john
Member level 1
hi
The reset pin is not locked in global input, so due to the load the reset gets duplicated.
now in cpci inteferace consider the bidirection data and tri-sate enable pin. after flattening the design these two FFs( output data and tristate en) are taking different asychronous reset because of duplication of rst.
due to which i was not able place these two simulatenously into IOB. since IOB accepts only single reset input, however by specifying the load on rst pin rst duplication was avoided and the problem was solved.
load specified was more than 2500.
i want to know,is this a right method. what can be maximum load to be specified for a net not connected to global resourses.
what other means can i do to avoid this
thanks
The reset pin is not locked in global input, so due to the load the reset gets duplicated.
now in cpci inteferace consider the bidirection data and tri-sate enable pin. after flattening the design these two FFs( output data and tristate en) are taking different asychronous reset because of duplication of rst.
due to which i was not able place these two simulatenously into IOB. since IOB accepts only single reset input, however by specifying the load on rst pin rst duplication was avoided and the problem was solved.
load specified was more than 2500.
i want to know,is this a right method. what can be maximum load to be specified for a net not connected to global resourses.
what other means can i do to avoid this
thanks
