logical effort of inverter in hspice

[kkantham]

logical effort of gates in spice

can any body tell me how to calculate logical effort , electrical effort and parasitic delay of an inverter or any other gate in hspice

i first calculated delay for one inverter which is 0.1ns . then i added another inverter to make h=1 and the delay now is 0.2ns now i know that gh=0.2ns-0.1ns=0.1ns

next how to calculate g and h from gh accuralety in hspice . can we plot the graph of delay vs fanout in hspice

i am using 45nm technology

 

[oermens]

hspice simulation logical effort

refer to weste&harris cmos vlsi design chapter 5.5.3