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Logical effort and parasitics with HSPICE

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akis

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Hello guys!

I have a big problem and i need some help. I im working on a project and i have to find the parasitics(p) and logical effort(g) of standard cells with HSPICE. I have read the book of Waste-Harris especially the chapter 5 but it didnt help me a lot. This is a sample code of AND2_X1.sp file as i take it from Nangate Cell Library:

.GLOBAL VDD
.GLOBAL VSS

********************************************************************************
* *
* Cellname: AND2_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Default. *
* *
* *
********************************************************************************
.SUBCKT AND2_X1 A1 A2 ZN VDD VSS
M_i_0 net_001 A1 net_000 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_5 VSS A2 net_001 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_11 ZN net_000 VSS VSS NMOS_VTL W=0.090000U L=0.050000U AS=0.004050P AD=0.004050P PS=0.180000U PD=0.180000U
M_i_18 net_000 A1 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_25 VDD A2 net_000 VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_31 ZN net_000 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
.ENDS

********************************************************************************
*
* END
*
********************************************************************************

Except from the parameters that i have to add to this code for simulation what else i have to add so i can compute the logical effort and the parasitics?
Please help me if you can because that is important for the next steps of my project. :???:
 

leo_o2

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I think you should read HSPICE manual.
Please add ".tran" for simulation and ".print" for output.
 

akis

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I read the manual of Hspice and this is the new version:

.OPTION POST
.INCLUDE 'C:\NangateOpenCellLibrary_PDKv1_3_v2009_07\NangateOpenCellLibrary_PDKv1_3_v2009_07\technology\models\hspice\hspice_ss.include'

.GLOBAL VDD
.GLOBAL VSS

********************************************************************************
* *
* Cellname: AND2_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Default. *
* *
* *
********************************************************************************
.SUBCKT AND2_X1 A1 A2 ZN VDD VSS
M_i_0 net_001 A1 net_000 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_5 VSS A2 net_001 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_11 ZN net_000 VSS VSS NMOS_VTL W=0.090000U L=0.050000U AS=0.004050P AD=0.004050P PS=0.180000U PD=0.180000U
M_i_18 net_000 A1 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_25 VDD A2 net_000 VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_31 ZN net_000 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
.ENDS

********************************************************************************
*
* END
*
********************************************************************************

Vdd VDD VSS 1.25V
Vin A1 VSS PULSE 0 1.25V 0ps 20ps 20ps 120ps 200ps
X1 A1 VSS B1 VDD VSS AND2_X1
X2 B1 VSS C1 VDD VSS AND2_X1
X3 C1 VSS D1 VDD VSS AND2_X1
X4 D1 VSS E1 VDD VSS AND2_X1
x5 E1 VSS F1 VDD VSS AND2_X1



.TRAN 1ps 200ps START=0ps

.END


Now i have a problem with the topology of the circuit.
I tried to create the topology of waste and harris's book example:

logeff.jpg

But hspice returned a lot of errors. Where should i connect the second input of every NAND gate?
 

leo_o2

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Do you set VSS to 0?
And please post the error information.
 

akis

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new code with VSS=0 and second input of AND to VDD but it returns the same errors...

.OPTION POST
.INCLUDE 'C:\NangateOpenCellLibrary_PDKv1_3_v2009_07\NangateOpenCellLibrary_PDKv1_3_v2009_07\technology\models\hspice\hspice_ss.include'

.GLOBAL VDD
.GLOBAL VSS=0

********************************************************************************
* *
* Cellname: AND2_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Default. *
* *
* *
********************************************************************************
.SUBCKT AND2_X1 A1 A2 ZN VDD VSS
M_i_0 net_001 A1 net_000 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_5 VSS A2 net_001 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_11 ZN net_000 VSS VSS NMOS_VTL W=0.090000U L=0.050000U AS=0.004050P AD=0.004050P PS=0.180000U PD=0.180000U
M_i_18 net_000 A1 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_25 VDD A2 net_000 VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_31 ZN net_000 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
.ENDS

********************************************************************************
*
* END
*
********************************************************************************

Vdd VDD VSS 1.25V
Vin A1 VSS PULSE 0 1.25V 0ps 20ps 20ps 120ps 200ps
X1 A1 VDD B1 VDD VSS AND2_X1
X2 B1 VDD C1 VDD VSS AND2_X1
X3 C1 VDD D1 VDD VSS AND2_X1
X4 D1 VDD E1 VDD VSS AND2_X1
x5 E1 VDD F1 VDD VSS AND2_X1



.TRAN 1ps 200ps START=0ps

.END


**error** no dc path to ground from node 0: a1
**error** no dc path to ground from node 0: b1
**error** no dc path to ground from node 0: c1
**error** no dc path to ground from node 0: d1
**error** no dc path to ground from node 0: e1
**error** no dc path to ground from node 0: f1
**error** no dc path to ground from node 0: vdd
**error** no dc path to ground from node 0: vss
**error** no dc path to ground from node 1: net_000
**error** no dc path to ground from node 1: net_001
**error** no dc path to ground from node 2: net_000
**error** no dc path to ground from node 2: net_001
**error** no dc path to ground from node 3: net_000
**error** no dc path to ground from node 3: net_001
**error** no dc path to ground from node 4: net_000
**error** no dc path to ground from node 4: net_001
**error** no dc path to ground from node 5: net_000
**error** no dc path to ground from node 5: net_001
 

keith1200rs

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Try

.GLOBAL VSS

Rather than

.GLOBAL VSS=0

And add

VG VSS 0 0

Keith
 
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leo_o2

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Agree with keith1200rs for correct gramma.
 

akis

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Thanks guys, now it runs without errors except this warning:
**warning** the following singular supplies were terminated to 1 meg resistor
supply node1 node2
vg 0:vss defined in subckt 0 0:0 defined in subckt 0

I think its not a big problem.
what exactly is VG in: VG VSS 0 0?

Now do you have any idea how to find parasitics and logical effort?
Should i put this in the code as shows the book of Waste&Harris?

.measure tpdr * rising propagation delay
+ TRIG v(c) VAL='SUPPLY/2' FALL=1
+ TARG v(d) VAL='SUPPLY/2' RISE=1
.measure tpdf * falling propagation delay
+ TRIG v(c) VAL='SUPPLY/2' RISE=1
+ TARG v(d) VAL='SUPPLY/2' FALL=1
.measure tpd param='(tpdr+tpdf)/2' * average propagation delay
.measure trise * rise time
+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1
+ TARG v(d) VAL='0.8*SUPPLY' RISE=1
.measure tfall * fall time
+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1
+ TARG v(d) VAL='0.2*SUPPLY' FALL=1
 

leo_o2

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That warning means a voltage source is floating.
I suggest you read thru the completed HSPICE manual for detailed syntax.
 

akis

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now i have no problem with the syntax.

but the main problem is how to find now the p and g?:!:

is this code useful for this problem?

.measure tpdr * rising propagation delay
+ TRIG v(c) VAL='SUPPLY/2' FALL=1
+ TARG v(d) VAL='SUPPLY/2' RISE=1
.measure tpdf * falling propagation delay
+ TRIG v(c) VAL='SUPPLY/2' RISE=1
+ TARG v(d) VAL='SUPPLY/2' FALL=1
.measure tpd param='(tpdr+tpdf)/2' * average propagation delay
.measure trise * rise time
+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1
+ TARG v(d) VAL='0.8*SUPPLY' RISE=1
.measure tfall * fall time
+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1
+ TARG v(d) VAL='0.2*SUPPLY' FALL=1
 

leo_o2

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I can't understand your meaning for "p and g".
The time measurement should be correct.
 

akis

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i mean p(parasitic delay) and g(logical effort) of a standard cell library.
Thats the main problem as i wrote at the first post.
 

erikl

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... how to find now the p and g?
It's all described in the Weste/Harris book, s. here: View attachment Logical_Effort.pdf .
You should run the same simulation analyses corresponding to Fig. 5.28 for fanOut 1..n (1..8 in Fig 5.28 (b) , maybe n=4 or 5 should be enough) ...
  • for your AND2
  • for the smallest INV
  • from their slopes ratio you'll get g
  • then do the same without any load after your DUT (i.e. without the X4, X5 gates)
  • then from their (AND2/INV slopes) ratio you'll get p
 

akis

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It's all described in the Weste/Harris book, s. here: View attachment 61439 .
You should run the same simulation analyses corresponding to Fig. 5.28 for fanOut 1..n (1..8 in Fig 5.28 (b) , maybe n=4 or 5 should be enough) ...
  • for your AND2
  • for the smallest INV
  • from their slopes ratio you'll get g
  • then do the same without any load after your DUT (i.e. without the X4, X5 gates)
  • then from their (AND2/INV slopes) ratio you'll get p
First of all the pdf file was damaged and i couldnt open it.
I read the book of waste-harris and i understood how to continue with this process.

I run this code:

.param SUPPLY=1.25V
.OPTION POST
.INCLUDE 'C:\NangateOpenCellLibrary_PDKv1_3_v2009_07\NangateOpenCellLibrary_PDKv1_3_v2009_07\technology\models\hspice\hspice_ss.include'

.GLOBAL VDD
.GLOBAL VSS

VG VSS 0 0


.SUBCKT AND2_X1 A1 A2 ZN VDD VSS
M_i_0 net_001 A1 net_000 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_5 VSS A2 net_001 VSS NMOS_VTL W=0.130000U L=0.050000U AS=0.008450P AD=0.008450P PS=0.260000U PD=0.260000U
M_i_11 ZN net_000 VSS VSS NMOS_VTL W=0.090000U L=0.050000U AS=0.004050P AD=0.004050P PS=0.180000U PD=0.180000U
M_i_18 net_000 A1 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_25 VDD A2 net_000 VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
M_i_31 ZN net_000 VDD VDD PMOS_VTL W=0.135000U L=0.050000U AS=0.009112P AD=0.009112P PS=0.270000U PD=0.270000U
.ENDS

********************************************************************************
*
* END
*
********************************************************************************

Vdd VDD VSS 'SUPPLY'
Vin A1 VSS=0 PULSE 0 'SUPPLY' 0ps 20ps 20ps 120ps 200ps
X1 A1 VDD B1 VDD VSS AND2_X1
X2 B1 VDD C1 VDD VSS AND2_X1
X3 C1 VDD D1 VDD VSS AND2_X1
X4 D1 VDD E1 VDD VSS AND2_X1
x5 E1 VDD F1 VDD VSS AND2_X1

.TRAN 1ps 200ps START=0ps

.END


is this code correct for logical effort?
Or i have to add new code?

Like this:

.measure tpdr * rising propagation delay
+ TRIG v(c) VAL='SUPPLY/2' FALL=1
+ TARG v(d) VAL='SUPPLY/2' RISE=1
.measure tpdf * falling propagation delay
+ TRIG v(c) VAL='SUPPLY/2' RISE=1
+ TARG v(d) VAL='SUPPLY/2' FALL=1
.measure tpd param='(tpdr+tpdf)/2' * average propagation delay
.measure trise * rise time
+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1
+ TARG v(d) VAL='0.8*SUPPLY' RISE=1
.measure tfall * fall time
+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1
+ TARG v(d) VAL='0.2*SUPPLY' FALL=1

Can you help me please, because i have to finish the project next monday.. :sad:

And finally how i will find the slopes that you describe above?

Thanks erikl.
 

erikl

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is this code correct for logical effort?
Or i have to add new code?
Of course you need the 'measure' statements. tpd is what you need for the ordinate dabs in FIG 5.28 (b) .

And finally how i will find the slopes that you describe above?
As I told you above. Read thoroughly!
 

akis

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I added this code:

.measure tpdr
+ trig v(c1) val='supply/2' fall=1
+ targ v(d1) val='supply/2' rise=1

.measure tpdf
+ trig v(c1) val='supply/2' rise=1
+ targ v(d1) val='supply/2' fall=1

.measure tpd param='(tpdr+tpdf)/2'


and .lis file doesnt return right value for tpd:

******
*
****** transient analysis tnom= 25.000 temp= 25.000
******
tpdr= -1.1874E-10 targ= 8.0431E-11 trig= 1.9917E-10
tpdf= failed targ= not found trig= 5.6558E-11
tpd= failed measure parameter failed

Is soething wrong with the code?
Or the topology of the circuit?
 

erikl

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Is soething wrong with the code? Or the topology of the circuit?
Circuit topology is ok (for fanOut=1). But for propagation delay measurement (tpd.) of a non-inverting gate (your AND2) you have to measure the tpdr from rise to rise and tpdf from fall to fall.

I really wonder if you know what you're doing?
 

akis

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I really wonder if you know what you're doing?
the truth is that hspice is not familiar to me..but i try it..the problem is that i havent plenty of time to learn all the hspice manual.

to the point now..

Circuit topology is ok (for fanOut=1). But for propagation delay measurement (tpd.) of a non-inverting gate (your AND2) you have to measure the tpdr from rise to rise and tpdf from fall to fall.
I tried this but again tpdf= failed and targ= not found therefore tpd failed.

I tried with inverter and NAND2 and i got tpdf tpdr and tpd without any problem.

whats going on with AND2?
 

erikl

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the truth is that hspice is not familiar to me..but i try it..the problem is that i havent plenty of time to learn all the hspice manual.
You don't need to learn all the hspice manual. But you should essentially know what you want to measure!

I tried this but again tpdf= failed and targ= not found therefore tpd failed.
Did you measure from rise=1 to rise=2 , and from fall=1 to fall=2 ?

I tried with inverter and NAND2 and i got tpdf tpdr and tpd without any problem.
Of course, because the measurement statements had been created for an (inverting) NAND gate!

whats going on with AND2?
This is a non-inverting gate, so you have to measure propagation delay times from first rise to second rise, resp. from first fall to second fall:

.measure tpdr
+ trig v(c1) val='supply/2' rise=1
+ targ v(d1) val='supply/2' rise=2

.measure tpdf
+ trig v(c1) val='supply/2' fall=1
+ targ v(d1) val='supply/2' fall=2
 

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