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Logic Synthesis for small rtl, correct synthesis netlist

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engr

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Hi all,

I am doing logic synthesis for small rtl, i created dc scripts for it and ran dc, i seen timing, none of timing paths vilolated.

Area constraints is violates, since i set max area to 0.

What are the the other things i have to look at , to conclude my synthesis netlist is correct apart from timing and area constains.

i have to look at netlist for any reason, to find out any issues in netlist
 

arjun1110

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Re: Logic Synthesis

>>What are the the other things i have to look at , to conclude my synthesis netlist is correct apart from timing and area constains.

Do LEC(Logical Equivalent Check) between RTL and Netlist to check both the netlist are equal.

Regards.
 

Syswip

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Re: Logic Synthesis

Hi engr,

After compile you should run and analyze several commands:

check_design
check_timing
report_constraint -all_violators
report_timing -loops

These are more important things to be checked.
 

engr

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Re: Logic Synthesis

I have generated reports for all the above said

check_design
check_timing
report_constraint -all_violators
report_timing -loops
everything fine regards to above commands , and i also did formal verifcation of rtl and netlist, its passing.

is there any thing that i have look at

Thanks in advance
 

engr

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Re: Logic Synthesis

i am looking at the synthesis reports and concluding my synthesis is corect, is this corect way or should also look at netlist and check something there manually
 

Syswip

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Re: Logic Synthesis

No you don't need to check netlist manually.

The only thing you can do try to simulate your netlist. And that's it. You're done.
 

engr

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Re: Logic Synthesis

try to simulate netlist?
Can you please elaborate, what it meant by simulating netlist ?

Thanks in Advance
 

Syswip

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Re: Logic Synthesis

what it meant by simulating netlist ?

The same as simulating RTL :D
Change RTL by netlist, include Libs and run your verification as you did during RTL.
You verification environment should be designed to support timing simulation.
 

aaronhe

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Logic Synthesis

If you have spyglass, you can run it to check your netlist's robustness
 

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