Logic levels in rtl design

[sachinkhati]

Hi,

i would like to know How do you define the max number of logic levels in a RTL design i.e before synthesizing how can we decide that we will code RTL in such a way that the number of logic levels does not exceed certain limit (3 or 4 or 5) .

While coding RTL we only consider the design to be functionally correct, So what should be the approach for RTL coding so that the design satisfies our logic level requirement as well.

 

[sivamani]

What do mean by logic level?Are u talking about voltage std like LVCMOS33 or LVCMOS25 etc?If it is yes that you need to specify in UCF will be considered after synthesis..

 

[amitjagtap]

As told in RTL coding we code only Logic details or functionlity...Logic levels are physical properties of each line/signal..that is not related to functionlity..this depends on FPGA individual banks... and IO capability.