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But these documents do not explain how a hazard in a reset path can produce an issue. Can anyone please answer how the presence of a logic (AND gate or OR gate) in front of asynchronous reset can produce a glitch. How is this glitch harmful?
To simplify things lets look at the below example :
you are havinig a active-high reset to a FF which means when ever reset is HIGH, you will reset the Flop.
Now you have introduced a AND gate i.e. RESET_NEW = RESET & CONTROL
Intention is that we want to have RESET = 1 and CONTROL = 1 then only we want to do a asycnronous reset to the Flop. The arrival times to the AND gate will vary and if so what will happen, lets assume that CONTROL arrives early and RESET arrives 200 ps later.
CONTROL changing from 0 to 1 and RESET changing from 1 to 0, because of this arrival time discripancy, you will see a glitch which is of 200 ps. If the Flop is able to detect the glitch on the RESET_NEW, it will reset the flop
I have written down the example quickly, Let me know if there any further questions.
To simplify things lets look at the below example :
you are havinig a active-high reset to a FF which means when ever reset is HIGH, you will reset the Flop.
Now you have introduced a AND gate i.e. RESET_NEW = RESET & CONTROL
Intention is that we want to have RESET = 1 and CONTROL = 1 then only we want to do a asycnronous reset to the Flop. The arrival times to the AND gate will vary and if so what will happen, lets assume that CONTROL arrives early and RESET arrives 200 ps later.
CONTROL changing from 0 to 1 and RESET changing from 1 to 0, because of this arrival time discripancy, you will see a glitch which is of 200 ps. If the Flop is able to detect the glitch on the RESET_NEW, it will reset the flop
I have written down the example quickly, Let me know if there any further questions.
why do you want to use glitch as real asynchronous reset to FF, think of this and may be you should start calling it with a different name if it was intentional
why do you want to use glitch as real asynchronous reset to FF, think of this and may be you should start calling it with a different name if it was intentional
I have a 3 input AND gate whose inputs are driven by three different asynchronous resets. Each of these three asynchronous resets are inverted by an inverter and sent to one of the inputs of this three input AND gate. The output of this three input AND gate is sent as an active low reset to a FIFO. Will this cause a reset glitch issue? If yes, please let me know how.
I have a 3 input AND gate whose inputs are driven by three different asynchronous resets. Each of these three asynchronous resets are inverted by an inverter and sent to one of the inputs of this three input AND gate. The output of this three input AND gate is sent as an active low reset to a FIFO. Will this cause a reset glitch issue? If yes, please let me know how.
the above scenario is completely legal, i do not think glitches are expected because of the addition of the AND gate, the reset to the flop will only be deasserted as a function of the last reset signal to change
naturally, timing would have to be closed for flop recovery and removal from all sources.
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