davorin said:Hmm..don´understand your question correctly...
For me a design is ready when it is synthesizable and then your software tells you at the end what resources it needs (o;
Or am I missing something here?
davorin said:4. Convince the others to go with a larger device than intended anyway. FPGA designs can make addictive and people therefore tend to try put everything in it...believe me (o; So always good not only to have LEs spare but also some 20/30 pins...
You can consult an application note from xilinx, VHDL tips for arithmetic operation, it gives you some examples on writing arithmetic functions (adders, magnitude comparators,...etc) and they are evaluating the number of LUT it will need. Basicly ton sum two numbers described with 4 bits for example, without taking care of the overflow, you need 4 LUT. You can do the same estimation for the other blocs you have in your design.
Hope it help you