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Logic estimation in FPGA?

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nagraj

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estimer ressource fpga design

How can designer roughly estimate number of macrocells needed,once design is ready...?
 

davorin

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Hmm..don´understand your question correctly...

For me a design is ready when it is synthesizable and then your software tells you at the end what resources it needs (o;

Or am I missing something here?
 

nagraj

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davorin said:
Hmm..don´understand your question correctly...

For me a design is ready when it is synthesizable and then your software tells you at the end what resources it needs (o;

Or am I missing something here?

Well thats my understanding too...But I had problem like which CPLD/FPGA series to be choosen for schematic drawing of system design.
So,If I could able to estimate number of macrocells based on registers,counters involved in the design...that could save lot of time for product development..I hope this is more clear...
 

davorin

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You can draw schematics first but never do any pcb design before FPGA implementation (o;

You could do the following:

1. Always choose a package which fits several devices with different LEs like for example ep1c3t144 which can be replaced with ep1c6t144.

2. Do some test designs with simple register/counter setups and see how resources are used. Most probably different for different manufacturers.

3. Check some application notes which best fit your application and try to synthesize them. If your application is a collection of several designs you can easily add the resulting figures.

4. Convince the others to go with a larger device than intended anyway. FPGA designs can make addictive and people therefore tend to try put everything in it...believe me (o; So always good not only to have LEs spare but also some 20/30 pins...
 

skynet

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if you want to know how much logic u going to use.. count ur flip flop u going to use + 10% extra.... that should be do it... for example, 10 bit counter will consume 10 macrocells
 

skynet

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macrocell or LE.. or whatever.. it just a naming problem.. right??? xilinx using CLB, n altera using LE..... so what is the different between the architecture?? speed?? density?? when come to FPGA/CPLD design, everything come to the same question.. how many D flip flop are needed.
 

kilone

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davorin said:
4. Convince the others to go with a larger device than intended anyway. FPGA designs can make addictive and people therefore tend to try put everything in it...believe me (o; So always good not only to have LEs spare but also some 20/30 pins...

That's really what I am experiencing... My FPGA has been attached with
2-DSPs,1 CPU, 2 U-Port, 4 ASICs, and now they want more...

Actually, logic estimation inside FPGA become more and more confusing,
especially after the advent of the high-end FPGA devices embedded with
BlockRAM/Multipliers/CPU Cores.

One thing to remember, a larger device from the start will make you
sleep well... :)
 

jacklalo020

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Hi,
You can consult an application note from xilinx, VHDL tips for arithmetic operation, it gives you some examples on writing arithmetic functions (adders, magnitude comparators,...etc) and they are evaluating the number of LUT it will need. Basicly ton sum two numbers described with 4 bits for example, without taking care of the overflow, you need 4 LUT. You can do the same estimation for the other blocs you have in your design.
Hope it help you
 

nagraj

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jacklalo020 said:
Hi,
You can consult an application note from xilinx, VHDL tips for arithmetic operation, it gives you some examples on writing arithmetic functions (adders, magnitude comparators,...etc) and they are evaluating the number of LUT it will need. Basicly ton sum two numbers described with 4 bits for example, without taking care of the overflow, you need 4 LUT. You can do the same estimation for the other blocs you have in your design.
Hope it help you

This seems to be interesting can you send the link please or search data to be given in xilinx...the search gave lot of results with your tip..
 

ashishjindal76

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hi

After u have synthesised ur design the synthesis tool gives u the complete report regarding the resources that it had used

bye
ashish
 

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