Logic equivalence checking

[sun_ray]

1. What are the constraints for LEC?

2. Is it the do file that is generated after synthesis for doing LEC sufficient to do LEC?

 

[hbeck]

1. What are the constraints for LEC?

2. Is it the do file that is generated after synthesis for doing LEC sufficient to do LEC?

If you use the design compiler for synthesis you need to activate the generation of a *.svf helpfile (contains all optimizations, renamings,...) that is necessary to find "compare" points.
Then you read in the synthesized netlist and of course the reference design (vhdl or verilog source) and start the LEC. Thats it!

 

[sam536]

LEC doesnt support .SVF generated from the DC.

---------- Post added at 10:52 ---------- Previous post was at 10:48 ----------



Constraints depends on the stage of LEC .

1. RTL to Pre-scan : no constraints. Jst read the design, map and compare.
2. Pre-Scan vs Post-Scan : Test constraints to mask the test logic. Map and compare.
3. Post-scan vs Post routed /CTS netlist ; No constraints.

Do file is nothing but your own way of generating the comamnds.

1. Set the log file
2. Read the .lib
3. Read the golden and revised files.
4. Set the mapping rules.
5. Compare.
6. write the reports.

If you have automated flow for generating do file for LEC, thats good to start with.

If you are using formality for Formal verification , SVF file is useful , where as LEC doesnt support SVF constructs.

Regards,
Sam

 

[sun_ray]

What is the command to generate the do file? I think it can be generated only by Cadence RTL Compiler and not from Synopsys Design Compiler.