Lockup Latches Usage in DFT

[Varun124]

Hi Guys,

I am working on lockup latch in genus tool and when I am adding a negative latch between pos edge clock and neg edge flop to reduce half delay hold violation problem in shift path, why cant we add lockup latch for neg edge to posedge. And we consider shift cycle instead of shift period .

Thanks in Advance

 

[BradtheRad]

Perhaps you can place an invert-gate in a strategic spot? If that causes unacceptable delay, then it may become necessary for you to create a latch that works the way you want, by assembling it from individual gates (AND, NAND, OR, NOR, invert).

 

[Varun124]

Perhaps you can place an invert-gate in a strategic spot? If that causes unacceptable delay, then it may become necessary for you to create a latch that works the way you want, by assembling it from individual gates (AND, NAND, OR, NOR, invert).

Hi BradtheRad,
Sorry when I read through documents, it says we need to add lockup latches for posedge to neg Edge but not other ways and I understood that posedge to negedge it will be same cycle whereas negedge to posedge it will be different cycle. But my
question was why we take cycle instead of delay. If u consider delay both posedge to negedge and negedge to posedge it will have same delay.

 

[VLSI17]

most of the ATPG tools are cycle based and not event based to my knowledge . So, they consider pos-edge to pos-edge as 1 cycle . So, -ve followed by +ve will be considered as 2 cycles . +ve followed by -ve is considered as single cycle .

request anyone who thinks my understanding is wrong to correct me