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It is supposed to tell you when the PLL is close enough to its target frequency that you can safely switch over and start using it for your clock. The problem is that there are many ways to create this signal and not all of them operate properly under all use cases. You really want to filter this signal and let your cpu read it as a status bit before it switches the clocks.
Capture time increases as SNR decreases among other design factors, so predicting when locked when switching often requires a lock detector.
If signal drops out due to fading loss, lock detector is needed. If using simple PLL synthesis with clean signals, it may not be needed except for fault detection reasons.