For verilog on Altera you can use $readmem (maybe the others too). Five years ago this was a bit dangerous as it would fail to work in rare cases, but also not post a warning. I used this to store the FPGA software memory-map on the FPGA, along with information about device utilization and timing. The feature was non-critical, and only used by myself for debugging, so the tool issues were not a large concern.
Xilinx FPGAs have a second, non-fabric accessible port to access BRAM and other non-fabric accessible RAMs (eg, the LUTs). They can be accessed through the ICAP port if needed. I don't recall what limits there are for this.