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I know Quartus II gives you the option to use HEX/MIF file for memory initialization - and I understand how such a thing is be possible for a LUT based RAM.
But how is it done for a BRAM ?
Writing information to a BRAM is done through its ports - one cell at a time.
When using default value for BRAM, the values are included in the bitstream. During the configuration phase, the FPGA sets the value of the BRAM from the bitstream. After the configuration phase, the BRAM is accessible through its port.
Well,
If it's being programmed - it makes sense that it's part of the bitstream...no surprise here.
But I thought that a BRAM is a highly optimized silicone area in the chip which has special access circuitry (somewhat similar to the access circuitry found on IC memory chip) - without individual cell access as with a LUT.
Without asking altera themselves, I doubt you will find anyone who knows how. And I doubt altera will tell you (this is probably all part of patents or secret in house magic they need to protect)
Functionally it's a huge shift register through all BRAM cells, along with the other configuration information streamed into the BRAM block. For me it's sufficient to know that we can rely on the feature. Knowing "how" it's done on a transistor level would be interesting for a FPGA chip designer, but I'm none and I guess you neither.
For verilog on Altera you can use $readmem (maybe the others too). Five years ago this was a bit dangerous as it would fail to work in rare cases, but also not post a warning. I used this to store the FPGA software memory-map on the FPGA, along with information about device utilization and timing. The feature was non-critical, and only used by myself for debugging, so the tool issues were not a large concern.
Xilinx FPGAs have a second, non-fabric accessible port to access BRAM and other non-fabric accessible RAMs (eg, the LUTs). They can be accessed through the ICAP port if needed. I don't recall what limits there are for this.
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