load design in verdi

[ricksanchez]

How to load a design in verdi and run simulation when there are both verilog and vhdl files in the design?

 

[FvM]

I presume it supports mixed language HDL simulation as any other simulator, presumed it's covered by your license. Instantiation of Verilog modules in VHDL design and vice versa should be described in the manual.