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Both U2 and U3 are single rails supply op amps. Because they cannot generate negative voltages, a virtual ground is needed. And that is what the VR1 and VR3 are for. Virtual ground should be approximately Vss/2. In your circuit it is probably essential to have the capability to change the virtual ground level and therefore there are pots instead of fixed resistors.
So to answer your second question - I believe they are necessary.
How is it possible to have variable S+ input when the voltage gets fixed just before it enters amplifier? It looks like to me that IN+ input will always be same voltage as VR1, why is that?
The voltage does not get fixed - there is a 20k pull-up/pull-down resistor. Let's say there is a sine wave 25mVpp (+5/-5mV) on the S+ input. The VR1 with 20k resistor simply add DC offset of approximately 2.5V so after the VR1 the square wave will be still 25mVpp but with 2.5V DC offset, which is what is required by a single rail amplifier.
I can't get it in simulation, I tried to build only DC offset of the circuit, but in my simulation result there is no DC offset, there are attachments in the post, please tell me, what is wrong with my scheme?
you need an extra resistors resistor connected between R6/R7 node and L2/R5/C2 node. The value should be fairly high around 10-68k. I would also change the values of R6/R7 divider to something in a region of 10s of kOhms.
Last thing is where is the load? The output is not connected to anything. Calculate the input impedance of your opamp and make it your load.
1. you need an extra resistors resistor connected between R6/R7 node and L2/R5/C2 node.
DONE
2.I would also change the values of R6/R7 divider to something in a region of 10s of kOhms.
DONE
3.Last thing is where is the load? The output is not connected to anything. Calculate the input impedance of your opamp and make it your load.
DONE
still can't get DC offset on input sine wave. the scheme & simulation results are in attachement, I've also added the output impedance of the load cell(350ohms, although don't know if it's any use...). in simulation result "V4" and "out" are same, they are overlapping...
why can't I get DC offset?
and to elaborate on your answer before("In your circuit it is probably essential to have the capability to change the virtual ground level and therefore there are pots instead of fixed resistors.So to answer your second question - I believe they are necessary.)
- basically I could without VR3, couldn't I?
if you change the Sine DC offset to 2V, the output is still the same!
that should not happen, because if the load cell S+ output has for example 10mV DC and some kind of AC component, the DC component will be ignored??? :?::?::?::?::?::?::?::?:
does not make any sense to me. I've attached a scheme and simulation in Multisim. Offset of AC source is set to 2V so the graph is oscilating around 2V, if I change it to 0V it will oscilate around 0V and pot R1 will have no effect on it!!!?????
As far as I know a load cell output will rarely resemble a pure sine wave. It will typically have some dc component and some ac slowly changing component. In this is the case here then you cannot have a dc blocking capacitor - that's why the schematic from your original post has not got one.
As far as simulation goes you need to know a bit more what exactly there is in the load cell you are trying to simulate to simulate it properly. Substituting it with a voltage source is too much of simplification.
Perhaps a high impedance voltage source would be closer but unfortunately without knowing load cells parameters it is only a guesswork.
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