Lms adaptive filter using dspic33f code error

Hello everyone,
I'm using dspic33fj128gp802 to background noise cancellation project. What i did was i'm taking the input from a microphone(headphone mic) as my input(In[]) and I'm giving my desire input by delaying some miliseconds then i have built a neural network using weights and updating weights. I tried this using simulink in matlab and it worked really well.
I checked this in lab and it didn't work. Then i gave Y=X in the coding and checked whether my circuit is working. It worked. So i realize it is a problem of my coding. This is a LMS adaptive filter and please help me if there is anything wrong in my code. I have uploaded all my files. I have used mplab and c30 compiler. This is a big help.
thank you

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#include "p33fxxxx.h"
#include "dsp.h"
#include "..\h\adcdacDrv.h"
#include <math.h>
#include <libpic30.h>

//contants
#define beta 0.01 //convergence rate
#define N 31 //order of filter
#define NS 40 //number of samples
//#define Fs 8000 //sampling frequency
#define pi 3.1415926


//Macros for Configuration Fuse Registers:
//Invoke macros to set up device configuration fuse registers.
//The fuses will select the oscillator source, power-up timers, watch-dog
//timers etc. The macros are defined within the device
//header files. The configuration fuse registers reside in Flash memory.



// Internal FRC Oscillator
_FOSCSEL(FNOSC_FRC); // FRC Oscillator
_FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_NONE);
// Clock Switching is enabled and Fail Safe Clock Monitor is disabled
// OSC2 Pin Function: OSC2 is Clock Output
// Primary Oscillator Mode: Disabled

_FWDT(FWDTEN_OFF); // Watchdog Timer Enabled/disabled by user software
// (LPRC can be disabled by clearing SWDTEN bit in RCON register

//void measuring_y(unsigned int value_y);


int main (void)
{
// Configure Oscillator to operate the device at 40MIPS
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// Fosc= 7.37M*43/(2*2)=79.22Mhz for ~40MIPS input clock
PLLFBD=41; // M=43
CLKDIVbits.PLLPOST=0; // N1=2
CLKDIVbits.PLLPRE=0; // N2=2
OSCTUN=0; // Tune FRC oscillator, if FRC is used

// Disable Watch Dog Timer
RCONbits.SWDTEN=0;

// Clock switch to incorporate PLL
__builtin_write_OSCCONH(0x01); // Initiate Clock Switch to
// FRC with PLL (NOSC=0b001)
__builtin_write_OSCCONL(0x01); // Start clock switching
while (OSCCONbits.COSC != 0b001); // Wait for Clock switch to occur

// Wait for PLL to lock
while(OSCCONbits.LOCK!=1) {};


initAdc(); // Initialize the A/D converter to convert Channel 4
initDac(); // Initialize the D/A converter
initDma0(); // Initialize the DMA controller to buffer ADC data in conversion order
initTmr3(); // Initialize the Timer to generate sampling event for ADC

extern fractional BufferA[NUMSAMP]; // Ping pong buffer A
extern fractional BufferB[NUMSAMP]; // Ping pong buffer B
extern unsigned int DmaBuffer; // DMA flag
extern int flag; // Flag

int i;

double X;
double Y;
//float W0,W1=0,W2=0;

//float a1 = -0.53195317487280547; //Coefficients
//float a2 = 0.98711627632416965;
//float b0 = 0.99355813816208483;
//float b1 = -0.53195317487280547;
//float b2 = 0.99355813816208483;
long j;
long t;
double D;
double E;
double W[N+1] = {0.0};
double In[N+1] = {0.0};


while (1) // Loop Endlessly - Execution is interrupt driven
{
if(flag)
{


for(i = 0; i < NUMSAMP; i++)
{
while(DAC1STATbits.REMPTY != 1);// Wait for D/A conversion
if(DmaBuffer == 0){

X = (BufferA);


for (t = 0; t < NS; t++) //start adaptive algorithm
{
In[0] = X; //new noise sample (**from port B**)
//__delay_ms(100);
__delay32(100);
D = X; //desired signal (**delay and give from port B**)
Y = 0; //filter’output set to zero (output from port D)

for (j = 0; j <= N; j++)
{
Y = Y +(W[j] * In[j]); //calculate filter output(equation in research note)
E = D - Y; //calculate error signal(error output is not needed)

for (j = N; j >= 0; j--)
{
W[j] = W[j] + (beta*E*In[j]); //(updating filter coe. as in the equ. )
if (j != 0)
In[j] = In[j-1]; //update data sample

}
}
}



//W0 = (X) - (a1*W1) - (a2*W2);
//Y = (b0*W0) + (b1*W1) + (b2*W2);

DAC1RDAT = Y; // Load the DAC buffer with data

//W2 = W1;
//W1 = W0;

}


else{

X = (BufferB);
for (t = 0; t < NS; t++) //start adaptive algorithm
{
In[0] = X; //new noise sample (**from port B**)
//__delay_ms(100);
__delay32(100);
D = X; //desired signal (**delay and give from port B**)
Y = 0; //filter’output set to zero (output from port D)

for (j = 0; j <= N; j++)
{
Y = Y + (W[j]* In[j]); //calculate filter output(equation in research note)
E = D - Y; //calculate error signal(error output is not needed)

for (j = N; j >= 0; j--)
{
W[j] = W[j] + (beta*E*In[j]); //(updating filter coe. as in the equ. )
if (j != 0)
In[j] = In[j-1]; //update data sample
}
}
}

//W0 = (X) - (a1*W1) - (a2*W2);
//Y = (b0*W0) + (b1*W1) + (b2*W2);

DAC1RDAT = Y; // Load the DAC buffer with data

//W2 = W1;
//W1 = W0;

}

}
flag = 0;
}

}
return 0;

}