# LLC converter design issue

#### ivan_mateo

##### Member level 1
Hi everyone,

After reading some application notes from infineon and TI, I got some knowledge about design steps related to LLC converter. As you know, there is Q value and this value depends on load. As you increase load Q will increase and decreasing load, Q will decrease. Therefore gain curves yields, gain versus frequency. And gain function parameters are Ln,Q, fn. And there is three zone in gain graph, if the working point in inductive area, it is possible to achive ZVS. But I could not understand how to determine Q and Ln values. Documents have graph gain versus frequency in different Q and L values. Ok we need to choose our Ln and Q values, but how?

#### HULK_28

##### Newbie level 5
Hello ivan_mateo,

for helping you efficiently, could you please indicate more information about your project, like voltage output and power.
Is it for a DC supply or a battery charger?
Your input voltage is universal or US only?

Regards.

#### treez

##### Advanced Member level 5
Hi,
Well I think you are over-thinking it.
Take a look at AN 4151 by fairchild
The basic point about an LLC is that when you are switching at the upper resonant frequency [1/{rt(Lr.Cr)}], then the converter simply operates like an ideal transformer, and Vout/Vin = Ns/Np.
.....so if the load is anything from 20% 10 100%, then Vout/Vin = Ns/Np......you dont need me to tell you how attractive that is.

You will try and arrange it so that your LLC switches at the w0 frequency for your case of vout and load....(load being variable of course)

Though remember that if you are doing a Half Bridge LLC, then your “Vin” is only half of your “actual Vin”….because the half bridge LLC only presents half of the input bus voltage to the LLC stage at a time…..look at it in Ltspice and you will see what I mean.
So anyway, forget about Q for the moment…….and just plot out equation (6) of AN 4151…..ie “2nVo/Vin = {big expression in magnitude lines}
…….they use “2nVo/Vin” which for me is just off-putting…it should be “n.Vo/Vin “ and then you just rememeber that for a half bridge LLC, then Vin is half of the input bus voltage. For me that’s intuitive, because you are then dealing with the actual input voltage presented to the LLC stage.

Anyway plot out that expression…but re-arrange it first so that you plot “Vout vs frequency”.
At first, if you are pensive…just stuff in some values for Lr and Cr………stuff ‘em in till you get a sensible value for w0…something like 100kHz……..Then Pick a Lm value……obviously don’t pick something that gives you loads and loads of circulating magnetising current (for obvious reasons)….but then again……..dont pick a ridiculously high value for Lm…because if you do, then look at your Vout vs frequency graph….you will see that if you pick a very high Lm value….then your w0 frequency becomes pretty well the peak of the Vout vs frequency graph…which means you could easily end up in the capacitive region and blow your fets out of the lab….
So this is why you must plot out the Vout vs frequency graph…..stuff in values…and keep altering them till you get something sensible….there is no single right answer…many values of Lr and Cr give you 100khz and it’s a bit “six and two threes”, as to exactly which is right for you………Massage the Lm value a bit aswell…and get it nice.

Remember that you want to be a decent way clear of the capacitive region, so massage the Lr’s, Cr’s and Lm’s till you get it nice...the plot nice.

Here is an example attached, so you don’t even have to plot it all out…(sorry though..i may have succumbed and used “M = 2n.Vo/Vin”).
When yuouve plotted it..run the sim to check it.

....the only advice is that if you stop yourself doing it until you know absolutely how to do it...then you will never get started at all......stuff in some values...screw it up horribly...then clean the mess up and its job done.

- - - Updated - - -

oh and BTW, equation 6 is for a tightly wound transformer with low leakage, and an external Lr......if you have Lr in the transformer, then the gain is a bit higher....as AN4151 says.

#### Attachments

• 2.8 MB Views: 4
Last edited:
ivan_mateo

### ivan_mateo

points: 2

#### d123

##### Advanced Member level 5
Hi,

Some app notes make me mad (kidding, mostly) - the ones that provide formulas or require factors with no explanation so you spend another week looking for one term in the formula so as to complete it, and the ones that don't use brackets as much as might help people without a mathematical background...

Have you seen AND9408/D by OnSemi? Page 3 says:

Q = (√Lr/Cr)/Rac

Not sure if that helps.

treez

### treez

points: 2

#### treez

##### Advanced Member level 5
Pretty much the main point of LLC design….is to make sure that your w0 frequency is far enough away from the peak of the vout vs frequency graph so that you don’t inadvertently go into the capacitive region…eg during a transient or something………so ensure your w0 frequency is a good few khz above the peak of the vo vs freq graph.
Also, ensure that you achieve this without too much circulating magnetising current…low Lm means higher magnetising current….but you will need a good bit of magnetising current in order to get your w0 far enough above your peak of your “vo vs freq” graph.
Also, regarding Lr and Cr, you don’t want a ridiculously high Lr and ridiculously low Cr……..because like that you can get big overvoltages on Cr.

- - - Updated - - -

Also remember that you can look at the primary magnetising current on the simulator by putting in the relevant expression in the waveform window……ie something like i(pri) – (ns/np) * i(sec), but may be a plus depending on the sim’s view of the inductor current direction.
The magnetising current will be a bipolar triangle wave because the primary simply sees a square wave of magnitude Vin (remember that vin is half the input bus volts for a half bridge LLC)….the primary sees all of vin, because when switching at w0, the voltage of the Lr and Cr are equal but opposite in sign…..so they cancel each other out….leaving the entire input voltage to go across the primary.
Knowing the magnetising current can be handy, because you can tell if you’ve got enough magnetising current to discharge the Vds capacitance and thus give you zero voltage switching…..this is especially important at your highest switching frequency, where your magnetising current naturally reduces.

#### treez

##### Advanced Member level 5
We also see that when the LLC converter has high magnetising current, then this means that the vds capacitances get quickly discharged at the FET switching points…and thus your dead time should be less….but then again one usually settles for a general dead time which suits the majority of the load range.

#### ivan_mateo

##### Member level 1
Hello ivan_mateo,

for helping you efficiently, could you please indicate more information about your project, like voltage output and power.
Is it for a DC supply or a battery charger?
Your input voltage is universal or US only?

Regards.
Hi sorry for late response,

12V-25A. It will be DC supply. PFC stage input will be universal.

#### Easy peasy

##### Advanced Member level 5
Simple 2 switch fwd converter would work well here too ..

#### treez

##### Advanced Member level 5
Yes, here is a two tran fwd with sync rects......its a home brew sync rect circuit because off the shelf chips for this are terribly expensive.
Also, there is a sim which purely shows the sync rect logic by itself (for a 2TFC)

they are ltspice sims

- - - Updated - - -

Also, attached is the sync rect section of my SMPS course....

- - - Updated - - -

in fact, here is the link to the entire smps course

#### Attachments

• 15.7 KB Views: 0
• 8.1 KB Views: 0
• 2.4 MB Views: 0

#### HULK_28

##### Newbie level 5
Hi sorry for late response,

12V-25A. It will be DC supply. PFC stage input will be universal.
Ok ivan,

for this level of power, you can use this application note, very efficient for your need and easily editable for your output current:

https://www.onsemi.com/pub/Collateral/febfan7688_i00250a.pdf

If you have any questions for validate your adaptation, post here.
For 20A you can buy directly the evaluation board in digikey: https://www.digikey.fr/product-deta...0250A-GEVB/FEBFAN7688-I00250A-GEVB-ND/5618135

Regards.

#### HULK_28

##### Newbie level 5
on the shelf (Wurth elektronik), you will find the model of the transformer used in this application note.
This is often what can cause problems when you are not equipped to make this type of transformer.

https://www.we-online.com/catalog/en/WE-LLCR/

#### treez

##### Advanced Member level 5
Hi,
First you may want to consider the combination of LLC and sync rects…

The main problem with synchronous rectifiers is that when the SMPS goes into light load, then the output current can potentially reverse and build up to ruinously high levels, due to the sync rects turning on when you’d rather they wouldn’t……..with a two transistor forward, the build up of reverse current is delayed by the output inductor. This is why the two tran forward is quite good for use with sync rects.

The LLC converter, as you know, has no output inductor….and so when having sync rects, and in light load, the reverse current can build up much quicker with an LLC…this is why the LLC is not quite so suited to sync rects as a two tran forward.

- - - Updated - - -

...That FAN7688 of Hulk's looks great.

I see it uses secondary side controller...which means it will need an isolated offline flyback bias supply to provide power to it....also, it needs the current sense transformer.

There are other fairchild LLC chips which can mean you can do it from the primary side with less "extras" needed so to speak.

Though i confess that secondary side control is much better from a transient response point of view.

- - - Updated - - -

Also, in the schem on page 10 of Hulk’s kindly supplied LLC app note….
The primary side fet drives show a Schottky at D2 and D8.
….Ive never seen this before…but suppose it must be for sweeping out the minority carriers out of the PNP so that it can turn off quicker (?)
Also, the resistors at R1 and R12…they are obviously for preventing ringing at the fet gate….but why put them inside the base-emitter loop?...i mean , you dont really want to overvoltage the Base-emitters of those PNPs and you’ve more chance of doing that with R1 and R12 where they are. I think theyd be better off outside the base emitter loop…though I have to confess that where they are, they probably allow a slightly faster turn off of the PNP.

FAN 7688App note
https://www.onsemi.com/pub/Collateral/febfan7688_i00250a.pdf

#### treez

##### Advanced Member level 5
haaving said that, the FAN7688 has incorporated features to prevent light load reverse current in the sync rects.