(LINT-1) Warning: In design 'counter11', cell 'C58' does not drive any nets.

[windy7286]

when i use DC, i found there was a warning in the below module.

---

Code Verilog - [expand]
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module counter11 ( output logic [3:0] count,
                   input logic nreset, nready, clk);
                   
always_ff @ ( posedge clk, negedge nreset)
    if (~nreset)
      count <= 0;
     else
       if (count < 11 && ~nready)
       count <= count + 1;
       else 
    if (~nready)
          count <= 0;
endmodule

---

dc_shell> check_design
Warning: In design 'counter11', cell 'C58' does not drive any nets. (LINT-1)
1
I cannot find the mistake in the module.
Who can get me a hand?
many thanks

 

[morris_mano]

Try to change the 'if' condition as follows and see if it removes it.

if(!nreset)
[INDENT]count <= 0; [/INDENT]
else if ((nready) || (count == 10))
[INDENT]count <= 0;[/INDENT]
else 
[INDENT]count <= count + 1;[/INDENT]

 

[windy7286]

I have changed systemverilog file as you written. But the warrning still exit. info as below.

dc_shell> read_file -format sverilog ./clockgating/counter11.sv
Loading db file '/home/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPLL_Worst.db'
Loading db file '/home/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPLL_Best.db'
Loading db file '/home/esdcad/software/synopsys/linux/galaxy_C-2009.06-SP4/libraries/syn/gtech.db'
Loading db file '/home/esdcad/software/synopsys/linux/galaxy_C-2009.06-SP4/libraries/syn/standard.sldb'
Loading link library 'CORE9GPLL'
Loading link library 'CORE9GPLL'
Loading link library 'gtech'
Loading sverilog file '/home/username/clockgating/counter11.sv'
Detecting input file type automatically (-rtl or -netlist).
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/pf1e11/clockgating/counter11.sv

Inferred memory devices in process
in routine counter11 line 5 in file
'/home/pf1e11/clockgating/counter11.sv'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| count_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/pf1e11/clockgating/counter11.db:counter11'
Loaded 1 design.
Current design is 'counter11'.
counter11
dc_shell> check_design
Warning: In design 'counter11', cell 'C44' does not drive any nets. (LINT-1)
1


the warrning still exits. but cell name changes.

 

[morris_mano]

Look at your gate level netlist and see if you can track what signals are driving instance 'C44'.

Usually, in counter, if count value is small(say 7 for 4 bits) , then MSB is not toggling and you may get those kinds of warning. But it is not so in your case.

 

[windy7286]

Thanks your reply.
I still have a question. Could U tell me how to get gate level netlist and track signals?
I am a freshman.

many thanks.

 

[morris_mano]

I use Cadence RTL compiler(RC) and not so familiar with DC, but there must be a similar command like 'write_netlist' after you synthesize to output the netlist. In RC, we can view netlist schematic and there is a search for instance option, so it is really easy to track signals.

 

[vikadik]

Something in your code makes DC think that it needs a buffer at the end. Change your code.