chaitanya.531
Member level 1
Hey Folks,
plz
Need a little help here with my VHDL code.
I'm new to VHDL so please bear with me.
I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/rc5final.vhd" Line 41. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/rc5final.vhd" Line 44. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
code is
plz
Need a little help here with my VHDL code.
I'm new to VHDL so please bear with me.
I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/rc5final.vhd" Line 41. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/rc5final.vhd" Line 44. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
code is
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rc5final is
port (
din : in std_logic_vector(64 downto 1);
si : in std_logic_vector(32 downto 1);
encdec : in std_logic;
data_in : in std_logic;
clk : in std_logic ;
dout : out std_logic_vector(64 downto 1)
);
end ;
architecture Behavioral of rc5final is
component rc5round
port (
si : in std_logic_vector(32 downto 1); -- subkey
di : in std_logic_vector(64 downto 1); -- data in
do : out std_logic_vector(64 downto 1); -- data out
encdec :in std_logic;
data_in : in std_logic;
clk : in std_logic -- clk
);
end component;
signal da , db ,da1 ,db1 : std_logic_vector (32 downto 1);
signal di : std_logic_vector(64 downto 1);
signal doreg :std_logic_vector (64 downto 1);
begin
da <= din (64 downto 33);
db <= din(32 downto 1);
ed: process(clk,encdec)
begin
if (encdec ='0') then
da1 <= da+si;
db1 <= db+si after 10ns ;
di <= da1&db1;
r1: rc5round port map ( si,di,doreg,encdec,data_in,clk);
dout <= doreg;
else
r2: rc5round port map ( si,din,doreg,encdec,data_in,clk);
da1 <= doreg (64 downto 33)-si;
db1 <= doreg (32 downto 1)-si after 10ns;
dout <= da1&db1;
end if;
end process;
end Behavioral ;