Does any one are working on Library characterization methods?. On what stage the library characterization are implemented in digital design flow and what are effects of load and slew wrto this?.
It will be great help, if any can send the links or papers regarding this,...
library characterization is generally separated from typical ASIC design flow..The standard cell library generation itself requires well-defined flow..
Typically it contains development,characterization,view generation and view validation...
Load and slew do play a vital role in library characterization. designer must make sure that they select proper load and slew points so that the timing table is not extrapolated for most of the cases by synthesis and P&R tools
For standard cell based ASIC we design a number of basic primitives (like NAND,NOR, Inverter,Mux,etc). The layout and schematic design part of this is called Library Development.. For timing and power analysis you should have all the information regarding a particular cell (e.g, for given input slew and output load how much delay it should have and power also)..This part of the Library design procedure is called characterization, in which you calculate delay and power for each library primitive for given input slew and output capacitance range....