Liberate doesn't understand a finite state machine (more than 1 flops connected in a "complicated" way). Liberate understands multi-bit flops but not if you have flops connected in arbitrary fashion to design a standard cell block.
The only way is to write vectors for individual arcs making sure that you have a complete set. Also these will not be synthesizable as the synthesis tools wont understand these designs. They are done custom, characterization is custom and inserting into the design is also custom. Be it liberate or siliconsmart...none of these tools understand the state_tables of a complex block. the state_tables are for a different purpose.
So if there is a "real" advantage of doing a FSM in standard cells, then only it should be done. else it is better to write an RTL with individual flops and synthesizing it ....letting the timing tools take care of timing closure.