engiulio
Newbie level 1
Hi all,
I have a problem with the synthesis of leon3... I want to have the post-synthesis verilog to make simulation with modelsim, have the VCD and the SAIF, to use primetime for power report...
everything is ok but some module's names are too long and I can't write the DDC and primetime won't go... i tried to use change_names_rules -maxlength 32 in DC, but the module names doesn't change... if someone else had solved this problem I will thank him for a long time, because i need to graduate and I had to finish my master-thesys
Thanks
I have a problem with the synthesis of leon3... I want to have the post-synthesis verilog to make simulation with modelsim, have the VCD and the SAIF, to use primetime for power report...
everything is ok but some module's names are too long and I can't write the DDC and primetime won't go... i tried to use change_names_rules -maxlength 32 in DC, but the module names doesn't change... if someone else had solved this problem I will thank him for a long time, because i need to graduate and I had to finish my master-thesys
Thanks