Length Tolerance for Diff Pairs

[SughiRam P.]

How to calculate length matching tolerance for Differential pair signals???

Shall i take entire rise time as length tolerance or 1/10th of rise time as a tolerance????
:-?:-?:-?

 

[andre_luis]

It is strongly affected by signal bandwidth, and also depends up to specifications of device comunication driver you´re working.

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[SughiRam P.]

Thanq Andre....


Still I'm not clear with length tolerance calculation???


im seeking suffice for the above..


Can anyone clear me?? :???::???::???::???::???:

 

[marce]

https://www.edaboard.com/threads/213550/
a long discussion on diff pairs with lots of relevent links.

 

[andre_luis]

...Still I'm not clear with length tolerance calculation???...

You must provide more informations regarding scope of design you´re working.
Each comminication standards ( SATA / ETH / etc... ) have proper specifications.

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[marce]

As Andre has said you need to refer to the relevent specification for the signals.
From the previous discussion regarding diff pairs, on critical factor is keeping the signals the same electrical length for the extent of the diff pair routing.:?
That is correcting any length differences as soon after the discontinoutity as possible.
Regardless of the actual signal specification, the main thing I learned from the above threadis: the closer you can match the diff pair routes along ALL their length, the better. This is for EMC, signal integrity etc. So in future I am going fo a difference of 0mm difference for all diff pair routing, and will work my way down from that to the allowable tolerence relative to the signal specfications.

 

[SughiRam P.]

Tanq Andre and Marce,,,

Im clear tat there are several communication standards...

 

[nelsonys]

If your project do not have specific specs for deskewing, the rule of thumb is what you mentioned before 1/10 of the rise time. Consult your circuit designer for max tolerance as they might have certain spec for jitter tolerance. But still, you might need to calculate it first and compare your result with those given by circuit designer. Over-design may occur which causes you to over-compensate your differential pair length (taking up extra board space).

 

[SughiRam P.]

After some dig, i got answer. For diff pairs, there is a cross over voltage. Within that level both P and N should cross. Considering this and the trace environment we can calculate the exact allowable delay within pair.

 

[marce]

I realy dont understan your answer could you elaborate, as I have always worked from the specification related to the diff pair I am laying out. An when length matching either a physical length (mm) or a time difference is used, not a voltage.

 

[SughiRam P.]

See the attached Image. There is a cross over voltage(Circled in RED) for every differential signal. If P and N signals crossed within this level, it's fine. If P is delayed for some 'ps' then, skew between these two signals make cross over point above or below the allowable level. We have to make the cross over point within the specified level. The allowable timing skew can be calculated by simulating the signal.

 

[marce]

Yes I know how diff signals work, but as the allowable skew is given for each interface and copious notes by Dr Howard Johnson, Lee Richley etc on laying out diff pairs why make life complicated.

 

[FvM]

the allowable skew is given for each interface

Yes. At least I'm not aware of an interface standard specifying intra-pair skew in terms of a cross-over window. But of course the skew shows in common mode signal, eye-width of the differential and cross-over waveform of the single ended signals.

Unwanted common mode signal, related to generated electromagnetic interferences is in fact the main motivation for the strict intra-pair skew specifications in Gigabit standards like PCI express.