Length of transistors in Layout

[Shady Ahmed]

I am only used to designing in the schematic view without expecting the designs to be fabricated.

Now i am designing a chip to be fabricated, so , i am asking for some tips in schematic design that would help and make life easier in Layout and packaging phase, what to do and what not to do?

For instance: i heard that i should use the same transistor length for ALL MY DESIGN , otherwise it would cause troubles in layout phase? is that true?

 

[erikl]

i heard that i should use the same transistor length for ALL MY DESIGN , otherwise it would cause troubles in layout phase? is that true?

Not at all. Use the transistor models provided by the fab, and assign widths and lengths as you need. Depending on the models there will be min. and max. limits for both width and length for every model. If you need more than max. limit, parallelize (width, e.g. by fingering) resp. serialize (length) the devices.

 

[Shady Ahmed]

Ok, thanks for the help.

Any other layout tips ?

for ex: the feasible values of resistors and capacitors that i should stay within in the schematic such that it doesn't take up a large area on the layout?

Any thoughts are much appreciated.
Thanks for your time

 

[erikl]

Any other layout tips ?

for ex: the feasible values of resistors and capacitors that i should stay within in the schematic such that it doesn't take up a large area on the layout?

Resistors: this depends on your process. Usually between 10³ (l/w >≈ 1) and 10⁶ Ohm (area consumption).

Capacitors: also process dependent (availability of double poly, MIM). Usually 10^-14F ( > parasitics) - 10^-12F (area consumption).