left shifter in vhdl---illegal sequential statement error

[phobos1]

leftshifter in vhdl

library ieee;
use ieee.std_logic_1164.all;
entity ls is
port(a:in std_logic_vector(3 downto 0);
but std_logic_vector(3 downto 0);
clk: in std_logic);
end ls;
architecture arch_ls of ls is
begin
process(clk)
begin
if (clk='1' and clk'event) then
g:for i in 0 to 2 generate
b(0)<='0';
b(i+1)<=a(i);
end generate;
end if;
end process;
end arch_ls;


i am getting illegal sequential statement error
........ how can i define for statement within a if statement..........

 

[permute]

you want "loop" inside of a process. its for ... loop, and end loop;

 

[FvM]

b <= a(2 downto 0) & '0';