LEC -< what common problems, which Designers meet

[ivlsi]

Hi All,

What common problems, which are usually met during LEC (Logic Equivalent Check) check?

What are solutions?

Thank you!

 

[Plzhelp]

Generally there are 2 kinds of problem that you face when doing LEC. Aborts and Mismatches.
Aborts are when your logic cone is too huge, your tool will not be able to check for equivalency between the RTL/Netlist to Netlist. I mean, the tool will exhaust after certain amount of tries giving you an inconclusive result.
Mismatch is when you start getting Non Equivalencies between the RTL/Netlist to Netlist comparison.
For resolving Aborts you need to increase the effort level of the tool, include some cut points in the logic cone to reduce its size etc. These are certain basic things that can be done for resolving aborts.
Mismatches generally happens because of database Mismatches or due to optimization that happens while creating the netlist. The basic thing is to check whether the RTL being read and compared with its netlist during LEC s the same file used during creation of the netlist in synthesis.

With these basic checks I guess you are ready to go ahead with you LEC.

Cheers.

 

[d4red]

Generally there are 2 kinds of problem that you face when doing LEC. Aborts and Mismatches.
Aborts are when your logic cone is too huge, your tool will not be able to check for equivalency between the RTL/Netlist to Netlist. I mean, the tool will exhaust after certain amount of tries giving you an inconclusive result.
Mismatch is when you start getting Non Equivalencies between the RTL/Netlist to Netlist comparison.
For resolving Aborts you need to increase the effort level of the tool, include some cut points in the logic cone to reduce its size etc. These are certain basic things that can be done for resolving aborts.
Mismatches generally happens because of database Mismatches or due to optimization that happens while creating the netlist. The basic thing is to check whether the RTL being read and compared with its netlist during LEC s the same file used during creation of the netlist in synthesis.

With these basic checks I guess you are ready to go ahead with you LEC.

Cheers.

Thanks for the information. Can I ask how to do cut points? LEC does it or user has to do it?

 

[ivlsi]

What does it mean "cut point"?

 

[Plzhelp]

Hi guys,

Sorry for the late reply. Was little busy with my work.
Well, I hope you guys understand what logic cone is all about. With that assumption that you know about it, when logic cones become very big, the EC tool is not able to handle it and thus gives you aborts. In order to handle abort points, what we do is divide the logic cones into smaller parts. This division of large logic cones into smaller parts is generally known as inserting cut-points. It can be done by the user as well as the tools. Tools are getting smarter day by day.

Regards.

 

[rancho_trojan]

There is already an explanation on aborts above so let me explain a little about the mismatches/non-equivalencies.
95% of non-eqs are due to missing modelling directives. You might have used some commands for netlist optimization or for timing reasons during netlist generation. These will show up as non-eq points until you counter them using modelling directive sin your block_setup or do files. Most common ones include seq const, seq merge, seq redundancy, clock gating, latch transparency/folding and feedback. The remaining 5% might be real issues.

Most modelling directive issues can be resolved using analyze setup -verbose which adds flatten model commands for all the above mentioned common issues. Remaining ones could be resolved using analyze noneq <gate id> or just analyze noneq. This commands will analyze all non-eq pairs and give out a possible reason on why you are seeing a mismatch.