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Leakage currents in nano meter scale CMOS processes

hobbyiclearner

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Hi,

What are the leakage currents in nano-meter range CMOS processes used nowadays. Can anyone point me to relevant documentation pls?

Thanks and Regards,
Hobbyiclearner
 

t4_v

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It should be written in a process documentation. In 0.18 um, if I remember correctly, leakage currents for transistors are in range of single pA. In low process nodes, I do not remember, but I think it should be more.
 

hobbyiclearner

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OK. I wanted to know the leakage current mechanisms for nano meter scale processes - like 50 nm, 32 nm and so on. I dont have any pdks with me. Do you have / can you point me towards relevant documentation? is there any benchmark review paper on it that you may be aware of?

Thanks and Regards,
Hobbyiclearner
 

dick_freebird

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There are of course many papers and many foundry
marketing presentations showing anecdotal data (or
wishful thinking). Go fish around ieeexplore and
then go find those papers elsewhere, if you don't like
supporting publishers who pay their authors nothing.

When you get to the lower end of your range of
interest all bets are off. You could have SiO2 or
HfO2/SiX high-K dielectric and metal or poly gate
and set it all on bulk, epi or BOX and see as much
C current from gate tunneling as from drain
conduction. If you find reliability design info there
is probably some aging stuff that sets bounds for
leakage. It's getting uglier every generation. Best
to step back from the edge while you're learning.
 

hobbyiclearner

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Go fish around ieeexplore and
then go find those papers elsewhere, if you don't like
supporting publishers who pay their authors nothing.
OK. Pls. tell me any books which provide info. on 50nm/ 32nm leakage current. I will get it. (Books anyways give better explanations than papers)

Best to step back from the edge while you're learning.
Its work related; other than that there are papers (easily available) on the internet (on leakage current mechanisms) for the previous generation IC nodes. Since these are review papers, one gets all the leakage current phenomena collated at one place. If you are aware of any such review paper for the present day nodes, pls. point me towards it.

Regards,
Hobbyiclearner
 
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t4_v

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Pls. tell me any books which provide info. on 50nm/ 32nm leakage current.
Have you tried Baker? Maybe you will find info there as he updates his book. I read 3rd edition and there is 1um and 50 nm process which he uses for designing. Maybe there is also info about leakage in this 50 nm process.
 

danadakk

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I would advise, if this is actual device design focused, you contact the foundries directly as process
numbers, over time and engineering, evolve. Stuff in most books can be dated.


Regards, Dana.
 
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t4_v

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I would advise, if this is actual device design focused, you contact the foundries directly as process
numbers, over time and engineering, evolve. Stuff in most books can be dated.


Regards, Dana.
True. Good advice. Anyway, books or any resource is good just to give an rough idea.
 

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