Hi Johnny
Ok, thanks for the additional info. The fact that you'll build your storage array
with MOS-Caps makes life a lot easier
Ok, first we sum up the leakage for a MOS-Cap that have an effect on cell
retention here. The most important ones here will be sub-vt leakage of the
select device and the gate leakage of the storage cap. Ask the technology
people for measured values and collect also the cap/voltage characteristics
of your storage cap. Don't forget that a backbias for cell and selectdevice
can improve the cap value and reduce leakage. After you get those values
build a small model an try to simulate those values to check if leakage and
cap in the model are good enough (sometimes models are not tuned for those
parameters but others ...
)
Ok, now we build our sense amplifier. Your sense amp will be the most important
circuit as it is going to decide what info was stored in the cell. As mentioned in
my previous post this needs to be done very carefully. However in your design
the data will not be packed very dense as you will have a big storage cell and
therefore a lot of space for wiring, spacing ... Nevertheless I think it's important
for your studies that you know that if everything is getting smaller the whole
world changes and more effects come into play
(bitline-bitline coupling which
might lead to the idea of bitline-twisting), 3d capacitors have more leakage pathes
and so on. Simulate your sense amp with multiple numbers of bit's per bitline
to get a rough idea what happens if your adding more cap to the sense nodes
and how this affects sense amp performance. Here we come to a point where
one has also to decide how much cap for a single cell is needed ... Here you can
make your trade of ...
A smaller storage cap has multiple effects. Layout gets much more compact but
you might have to change bits per bitline and/or refreshtime because the signal
degrades much faster or your senseamp is not able to detect a signal anymore.
A bigger storage cap however gives you a bigger layout but might allow you to
increase selfrefresh time and/or increase the bits per bitline. Here you have
to make up your decision and define the bitline wordline architecture. If you're
making this decision, don't forget to take into account that you can actually build
a selfrefresh that refreshes more then one wordline ... refreshing two wordlines
at the same time halfs selfrefreshtime ... so don't forget this lever
Summing this up, you know how the charge is getting lost, you know what your
senseamp can do and all you have to do now is pick an architecture (bit/bitline,
wordlines, number of senseamp stripes, number of wordlines refreshed at
the same time). Defining such an architecture also has an effect on power
consumption. THe more senseamps (longer wordlines) the more sensecurrent
and also the wordline activationtime goes up, more refresh cycles mean more
powerconsumption ... Whatever you pick has an effect on how you need to set
the refreshtime ...
As I have never done such a DRAM I can't give hints on how to pick, as
the big ones I have been working on have much more limited degrees of
freedom. Cell-Cap is limited by trench or stackcell (around 20fF target value)
and area and power are the main optimisation goals ... all this is giving the
technology people much more headache than circuit designers
However, I would do the following to come up with a target. Simulate
the senseamp with multiple bits per bitline variants and different storage caps.
This gives you a minimum cell level you need to detect a zero or a one. The bits
per bitline together with your 256kB memory size give you a number of wordlines
you need to have. Then I would simulate the single cell with sub-vt and gate
leakage to find how long it takes for the storage cap to reach the values found
as senseamp limits. This basically is your minimum refreshtime and depends of
course how much storage cap per cell you are planing to use. Add some guard-
band to this value and pick a nicely "countable" number close to it
For the selfrefresh logic I would nevertheless recommend something that can
be soft programmed with fuses or testmodes so that, just in case, you can adjust
the selfrefresh time. This gives you the possiblity to increase or decrease the
timing to find limits of your core.
Have fun with your DRAM
Best Regards
Andi