LDPC decoder project of Open cores in verilog

[mrflibble]

Converting from fixed point to float is obviously the same kind of operation but in reverse. Multiply by appropriate scale factor.

So if you can go from fixed point to float, and back again, AND you have a function that takes a float input and spits out a float output (aka function in matlab) I would think you have all the required ingredients...

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Maybe I am misunderstanding what your problem is .. you could read this one and see if it clarifies things: Fixed-point arithmetic

 

[sougata_vlsi13]

I got the answer how to create the LUT of the quantization scheme ie the chi-function given in pdf page no-59/69 of that msc_draft_sep thesis report...the formula is chi=-ln[tanh(x/2)] and then converting that equivalent decimal into corresponding binary.But there are still few doubts in my mind.....

1.first one the LUT that is created it is based on feeding the value in normal binary....is it possible to provide the i/p from users side and that also when in signed format like -0.7538 and to get the o/p.

2.Second one the block diagram that is provided in the thesis report of functional unit in p no-53/63 is it the same one for fully parallel architecture or should i need to implement anything more.

3.what was my implementation i have provided in post no-4....am i going in the right way as per my requirement ie post no-4 as what was provided in the thesis report.

 

[mrflibble]

1.first one the LUT that is created it is based on feeding the value in normal binary....is it possible to provide the i/p from users side and that also when in signed format like -0.7538 and to get the o/p.

I have no idea what that means. Could you rephrase it? Do you mean if you can use signed input and output values? If yes, then yes. Signed binary (2's complement) is still binary, so a LUT will still do the job just fine.

2.Second one the block diagram that is provided in the thesis report of functional unit in p no-53/63 is it the same one for fully parallel architecture or should i need to implement anything more.

No opinion, as I didn't read the entire thesis.

3.what was my implementation i have provided in post no-4....am i going in the right way as per my requirement ie post no-4 as what was provided in the thesis report.

See 2. That thesis is 100+ pages, so no I didn't read it all. Parts of it look sort of interesting, but not right now for anything I am doing.

 

[sougata_vlsi13]

as per my doubt no -1 i want to ask if my input value is -0.8 and if i have to implement it in a LUT using its binary representation then should i need to represent it in 2's complement form....the value after conversion coming like that for 0.8 it is 11001100 for eight bit i/p so should i need to take the MSB sign bit bfore decimal point

 

[mrflibble]

I'd say google around a bit for "signed 2's complement fixed point" and see if that clarifies things. Because I think you may want to use 2's complement fixed point...

 

[sougata_vlsi13]

I got my answer about fixed point...but will this design of LDPC be fitted into the FPGA bcoz i think too many resources are utilizing...

 

[mrflibble]

Why do you ask us? Get designing, run a place & route of your design and see if it fits. From what I quickly skimmed from that thesis it doesn't look too resource intensive, certainly not the LUT portion for this function we've been on about. So I think the LUT part of it should be no problem. Not sure about the rest of your design.

 

[sougata_vlsi13]

@ mina magdy and others
I studied that thesis report according to the pdf of the "MSc_thesis of LDPC" and also understood the code about the VN_CN update provided by you.I think some part of that code is wrong which doesnt correspond to the functionality.
first of all the signal "reg [6:0] Input_RAM" is provided unnecessarily which dont appear later on and some signal such as sum_fifo and sign_ram_fifo is not showing proper output.Moreover the input ram_in[7:0] provided at the beginning doesnt depend on LLR bcoz even when i forcing the value without LLR also it is showing the correct output at the eps side???so can you once plz verify and revert back...Thanks

 

[sougata_vlsi13]

please anyone help me with the above doubt...i am eagerly waiting for reply

 

[sougata_vlsi13]

I am done with the LDPC FU part as well as the controller part of the design as specified in the above mentioned thesis report.Now in the main block diagram it is given that the controller is controlling the total unit along with the shuffle network and decoded message.I just want to know how should i interface my controller which is nothing but a fsm with the FU part means more precisely how should i pass on the values to RAM and ROM...plz help me