LDO structure question

[devop]

ieee ldo

Hi ,
a question about LDO here.
I saw a RF chip which embeded a LDO.Vsupply 2.7~5.5,Current 20mA.and there is only ONE capacitor Cbypass 22nF connect to Vbattery.

I thought the close-loop gain should be large,so why there is no Capacitor connect to Vout?if all the Cout are all designed in the chip,how large the capicitor area will be??


Can someone give me some opinion of the structure of the LDO.

And if I want to design a ldo for a rf chip,for Vsupply 2.7~5.5,Current 20mA,what other spec I should pay much attention?

 

[iamxo]

full on-chip cmos low-dropout voltage regulator

I think, because the LDO output current is not large, small than 20mA, so small output cap can be used to for charge storage.

 

[rajanarender_suram]

capacitor free ldo

what is the output voltage of the LDO, if the output voltage is much lower than 2.7 V(ie atleast less Vth of nmos) than they might have used nmos pass transistor and the output cap requirements will be lower

 

[devop]

milliken regulator

because there is no output vdd pin,I have no idea what is the output voltage............

 

[safwatonline]

ldo internal structure

because there is no output vdd pin,I have no idea what is the output voltage............

there are many LDOs with only on-chip decoupling, they work on small load current and have PSR worst than the ones with off-chip caps

 

[yjiang]

cmos internally compensated ldo

I think it is a capless LDO ,which use charge-pump

 

[kumard35b]

ka nang leung site:edaboard.com

the internal compensation is done inside the opamp.
The capacitor is made of mos transistor so that externally you don't need to connect a capacitor for loop compensation,however you need to have full stable operation a small amount of capacitor to be connected to the output pin to ensure the system in full stage operation.

It is capacitor less LDO

 

[devop]

ldo nmos output

Thanks all!
can somebody give me some paper about the capacitor less LDO

 

[edwintsu]

output noise ldo

Full On-Chip CMOS Low-Dropout Voltage Regulator
Milliken, R. J.; Silva-MartÃ?nez, J.; SÃ?nchez-Sinencio, E.
Circuits and Systems I: Regular Papers, IEEE Transactions on [Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on]
Volume 54, Issue 9, Sept. 2007 Page(s):1879 - 1890
Digital Object Identifier 10.1109/TCSI.2007.902615
Summary: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (ac) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-$mu$m CMOS technology, consuming only 65 $mu$A of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.
-------------------


-------------------
A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control requency Compensation
Ka Nang Leung, Member, IEEE, and Philip K. T. Mok, Senior Member, IEEE
A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factorcontrol frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6- m CMOS technology, and the active chip area is 568 m 541 m. The total error of the output voltage due to line and load variations is less than 0.25%, and the temperature coefficient is 38 ppm/ C. Moreover, the output voltage can recover within 2 s for full loadcurrent changes. The power-supply rejection ratio at 1 MHz is 30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 V/ Hz, respectively.
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[drabos]

study question for ldo board

Is it possible to use the bypass capacitor for the frequency compensation?

 

[peterwang]

nmos ldo ieee

I suggest the following material:

Current Efficient, Low Voltage, Low Dropout Regulators
by Gabriel A. Rinco-Mora


**broken link removed**

 

[peterwang]

applications of capless ldo

I suggest the following material:

Current Efficient, Low Voltage, Low Dropout Regulators
by Gabriel A. Rinco-Mora


**broken link removed**

I found out the link has been moved to :

**broken link removed**

 

[jt_rf]

capacitor-free ldo circuits

yes..it is a capacitor less LDO.

may or maynot have a chargepump.