Puppet123
Full Member level 6
I attempted to design a PMOS Pass Transistor LDO and obtained the following result.
I set the reference voltage to about 650mv and did a DC simulation.
The regulated voltage starts up and then dies as the VDD is ramped up.
What could be causing this ?
Thank you.
I set the reference voltage to about 650mv and did a DC simulation.
The regulated voltage starts up and then dies as the VDD is ramped up.
What could be causing this ?
Thank you.