LDO simulation by pcb

[snang]

Hello,
I have a question regarding the tapeout of a Low Dropout Regulator (LDO), so I’m posting here. I recently completed the tapeout of an LDO and am currently testing it by mounting the chip on a PCB. However, the regulation function of the LDO is not working properly.


When I test under light load conditions, the regulation seems to work well. But under heavy load, the regulation does not function correctly. Another issue is that other samples seem to regulate properly, unlike this one.


As mentioned above, I'm not fully confident that the LDO is operating correctly. Since this is my first tapeout, I'm seeking advice. What are some effective ways to verify whether the LDO is functioning properly?


Thank you.

 

[nitishn5]

Is it a case of poor load regulation or oscillations? More details please...
Do other samples work well on the same pcb?
Have you tried soldering the problem sample to reduce any track/parasitic resistances?

 

[sidun.av]

@snang
It would be useful to see your waveforms when LDO is not behaving properly.
Is it a capless or normal (cap is on PCB) LDO?
If everything looks fine in the simulation and you took into account the PCB and wirebond parasitics, then the problem must be in your PCB layout/ESR of the output cap. Please check that the output cap is placed close to the chip and has a low ESR.
Hopefully, that helps

 

[dick_freebird]

Instrument it up, all 4 terminals (ground is not just ground) and show good, just before and after "goes bad" and any soft slope in that regard.

PCB fed by banana jack wires needs an especially good input filter (aka decoupling at this level). Be sure to check supply current limit setting.