Hi Saro & Erikl,
Thanks, for now will consider DC gain @ Hz,
LDO output voltage is 3v and feedback loop current is 5u so Rf1 + rf2 =600k = Req
since we focus on DC output stage gain is gm3 x (rds || req)
Here is the list of gm & Gds for different currents i got through SPICE simulation..
and I am not capturing the behaviour you have mentioned..am i missing somthing here?
*********
id 2.9745u (cutoff)
gm 912p
gds 1.7537p
*********
id 4.1455m (saturation)
gm 55.399m
gds 272.49u
**********
As its seen, the gain @ zero current is dominated by "req" and gain @ saturation is high
compared to gain @ cutoff..its 180nm foundry process.
Thanks,