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LDO load transient response in the event of a sudden load change

promach

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See https://github.com/promach/LDO/tree/development for the LDO circuit.
Ignore the pictures inside README because they do not reflect the current circuit.

Without using external capacitor, could anyone advise how to solve this issue of LDO load transient response in the event of a sudden load change ?



 

danadakk

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Have you examined phase margin in design ?

Also most LDOs feed parts that have themselves bypass caps, so design should
handle C loading.

Lastly LDOs, depending on output stage design, have issues with C loading, in fact
spec min allowed ESR of the Cload cap. Eg. to decouple some of its phase shift
from control loop.


Regards, Dana.
 
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promach

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See the following test circuit and simulation result for phase margin:



 

danadakk

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With the 1 uF load C, no ESR in its model, you definitely have phase margin problems.

I am not a device designer, so will let someone else comment on best place in design
to add compensation. You of course have to decide on allowable C loading, and the
min ESR to "boost" the margin due to zero formed by cap.

What does design look like w/o Cload, that will indicate if specing ESR in Cload will
be enough to stabilize.


Regards, Dana.
 

promach

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The following bode plot is without CLoad.

Note that gain never reaches 0dB ......

 

d123

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Hi,

Erm... I don't know about IC design, as you know. A month or so ago I was mucking around with a discrete component (1.25V shunt ref of TLVH431, another shunt as inner supply regulator of 2V, pnp as enable, OA EA with OPA322, npn drive and pnp pass transistor rubbish but effective to overcome no model for LDO needed) linear nearly-LDO regulator of 10mA to 1.3A load in a simulator and added type 3 compensation to the EA and it seems to be very stable and have good transient response like load step, line regulation and so on, but then it is only in simulation-land so who knows... Certainly better behaviour than with no compensation. I think that's no use to you as you do not want external components, although onboard compensation R and C could be small or type 2 compensation?

As I said, way out of my depth so sorry if reply is naïve nonsense.
 

promach

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Even with 1us rise time and 1us fall time on Iout, the voltage overshoot and undershoot for Vout is still very serious

 

d123

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Hi,

Is there such a thing as a 'helper'/'booster' circuit, that is only enabled on sensing a sudden di/dt change to drive pass device harder and lock Vout to the preset level, or one that momentarily shifts Vref for EA fb to compensate for sharp rise in Iout?

Why can't you have hold-up caps with this LDO, is it internal to an IC or something?
 

promach

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@ danadakk

I managed to get the phase margin plot back to normal by using 1.8u instead of 18u for the length of M7, M8, M11 and M17
However, without output load capacitor CL, AC gain still could not reach 0dB.

I am still stucked with very bad load transient response

 

danadakk

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Your phase margin at 1 Mhz is really poor. If you look at T response it takes
~ 2 - 3 uS to settle, which makes sense for the 1 Mhz lousy phase margin.

You have to add a zero in response curve, starting at 100 Khz, to "lift" the
phase margin. 60 degrees if possible at 1 Mhz.

Not being a device designer I am not sure what stage to do that in.

https://www.d.umn.edu/~htang/ECE5211_doc_files/ECE5211_files/Chapter6_part1.pdf
'
https://www.analog.com/en/analog-di...-to-avoid-instability-capacitive-loading.html

http://cc.ee.nchu.edu.tw/~aiclab/teaching/AIC/lect10.pdf

http://cc.ee.nchu.edu.tw/~aiclab/teaching/AIC/lect10.pdf


Regards, Dana.
 

d123

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Hi,

Don't know, could be more than one reason, and no idea regarding W/L characteristics.

If it operates in the same way as a discrete EA - in the feedback loop, C and R in series from fb input to Vout, or perhaps C in parallel to RfbTop is another way to add a zero, in type 3 at least.
 

promach

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See the result using the known AC testbench setup (break feedback loop using large LC)








If I remove only C2 (removing C1 does not have observable effect) from the circuit, then see the following result :

 

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