LDO issue: for what supply values should i assign W/L ratios

[jutek]

LDO again

hello

i met this problem, when i changed input voltage from 1.3 to 3.3V.
The input voltage is also supply of the opamp. I designed the opamp for the lowest value of power supply 1.3V. Dropout voltage is 0.5V
When i change Vin to 2V and set feedback resistors to give 0.9V (Vref is 0.8 ) everything is ok yet.

But when i change it to 3.3V and let feedback be the same, transient response is very improper.

For what supply values i should assign W/L ratios? The opamp is simple p-input differential amplifier with active load.

Pass device is set to be in the saturation.

thanks in advantage

 

[paulux]

Re: LDO again

I guess the problem may be due to the saturation region of pass device. But accurate analysis of the problem could only be possible if the detailed schematics are available.

 

[jutek]

Re: LDO again

I guess the problem may be due to the saturation region of pass device. But accurate analysis of the problem could only be possible if the detailed schematics are available.

yes, the problem is, opamp's input transistors goes into triode region for the highest Vin=3.63V but for the smallest 1.3V is in the saturation. Opamp's gain is small then. How to assure quite constant voltage gain under different supply conditions.

thanks and regards

The circuit:




.PARAM W1=4u
.PARAM W3=4u
.PARAM W5=4u
.PARAM LM=4u
.PARAM LM1=4u
.PARAM W78=4u
.PARAM W6=10u

.PARAM VCM=0

.PARAM POWER=1.3V
.GLOBAL vdd gnd

VDD vdd gnd POWER

VCM 2 gnd vcm
Vin 1 2 ac=1

CL 3 gnd 40p (temporary)

XOP 1 2 3 OPAMP1

******************************************************
.SUBCKT OPAMP1 in+ in- out

M1 out in- S vdd CMOSP W=W1 L=LM
M2 2 in+ S vdd CMOSP W=W1 L=LM
M3 2 2 gnd gnd CMOSN W=W3 L=LM
M4 out 2 gnd gnd CMOSN W=W3 L=LM

M5 S bias vdd vdd CMOSP W=W5 L=LM

M6 bias bias vdd vdd CMOSP W=W6 L=LM1

M7 bias bias tst gnd CMOSN W=W78 L=LM1

M8 tst tst gnd gnd CMOSN W=W78 L=LM1

.ends

 

[paulux]

Re: LDO again

Thx reply.
Would you be possible to post your schematics with detailed sizes & biasing in jpg format to view?

 

[jutek]

Re: LDO again

Thx reply.
Would you be possible to post your schematics with detailed sizes & biasing in jpg format to view?

i drew the schematic in the LTSPICE. I don't simulate in it but in hspice

Wm12=70u, L=4u
Wm45=30u L=4u
Wm3=20u L=4u
Wm9=10m Lm9=0.5u
Wm6=4u Lm6=4u
Wm8=10u Lm8=4u

the problem is when Vdd goes to 3.63V M1,M2 work in triode (pure gain), when Vdd=1.3V M4 M5 are cutoff

the next problem is that pass device goes into triode region when Vdd=3.63
and also doesn't turn off completely

How to assure high output swing of this opamp, to not to add next stage. I think that's the problem

 

[paulux]

Re: LDO again

I guess of problem of triode/saturation is due to the biasing of your devices, you may need to choose other biasing or device sizes to avoid the above problems including cut-off problem.
You may need to change other structure of your amp to drive PMOS.
Hope this help.