LDO gain and bandwidth question

[PSG]

bandwidth of ldo

Hi,

I inherited some LDO design from a "departed" designer, and since this is my first LDO design (I've done some simple regulators before, but not like this) I have some pretty basic questions. Here are the basic specs first:

- the LDO is a step down from VIN=6.5V to VCC=5V (not much of an LDO really with 1.5V drop but anyhow)
- the LDO has 2 stages, an error amplifier and then a buffer connected to a PMOS pass device
- power consumption is not an issue (less than 0.5mA + output current)
- max output current is 100mA, min is 0
- 5V process
- the 6.5V input to the LDO will have some switching noise from another part of the circuit at up to 2.6MHz and there's a clock running off of a lower supply rail (VDD=1.8V derived from our VCC=5V output via another regulator) at up to 48MHz
- the LDO output comes out to a pin, there's a 1-2uF cap on it and I don't know what the customer does with it except they're limited to pulling 100mA from it

The design is done and the first silicon is working so this is just for my own understanding of LDO design. My questions are:

- how much gain should I have in the error amplifier?
- how much gain for the buffer?
- I'm guessing the total gain of the LDO will be the sum of the previous 2 gains
- what GBW should I have for both these opamps?
- I heard somewhere that for an LDO, having a phase margin of 45deg or more is not always necessary. Is that true? And if so, why?

Thanks for your time and hopefully your answers.

 

[anil.p]

ldo gain phase

gain of error amplifier is >60 db is sufficient

gain of buffer means its unity gain

and total loop gain is sum of error amplifier gain+power mos gain(gmp*rop)+feedback path gain

phase margin should be grater than 60 in order avoid ringing in output voltage waveform during transient conditions.