LDO AC analysis with low load

[jutek]

ldo ac analysis

Hello

I have a problem during simulating the LDO.

When i use high load RL=12 Vout=1.2V so Iout=100mA everything is correct, i can maintain the stability and the transient response is quite ok.

But when i use low load case, the open loop gain of the whole LDO decreases very much and has different shape than open loop gain of the opamp. The pass device is PMOS. Do i do sth wrong during the simulation or i should math gain, pole/zero position better.

I did the optimalization in the hspice and it didn't find the solution

Any ideas??

regards

 

[johnsmith101]

ldo analysis

LDO AC analysis is often difficult and inaccurate. AC analysis is a small-signal analysis linearized about a DC point. An LDO is more of a large signal device (large transients in output current for instance). Based on the loading of the LDO, the poles of the system can and will change significantly, Let's take the output pole (since I don't know the topology of your error amplifier). Keeping the output capacitor constant, the greater the output current, the higher the output pole frequency. As you can see, the output pole will vary substantially between the lightest and largest load conditions and can significantly impact the stability of the system.

I've found it is best to simulate LDOs using transient analyses and looking at the resulting overshoot. For example, you should run the following transient sims: +/- output current step, +/-Vsupply step, +/-reference step. And you should run these sims over all scenarios.

 

[jwfan]

ldo pass device operating point

You mean your DC gain decreased? Then you should check the operating point of your circuit, especially your pass device.

For light load, which means a larger load resistor, the output pole decreases. Which is not good for your phase margin. Pay attention to your ESR of output capacitor to make sure you have enough phase margin.

 

[jutek]

ldo stabilty check esr cap

yes, i understand that it's a small signal analysis

i use my own opamp behavioral model with two poles and one zero, differential input and dependent sources. i have good control of the gain, UGF and pole/zero location but under low load conditions strange things happen. Under high load conditions it don't occur. Maybe the model is not accurate?

But if the transient response is acceptable and AC open loop analysis says it shouldn't? I have that case, transient response is quite right but i can't read sth reasonable from AC

thanks and regards

Added after 7 minutes:

You mean your DC gain decreased? Then you should check the operating point of your circuit, especially your pass device

exactly, it dropped below zero. I use Vdd=3.3, Vout=1.2 so Vds =-2.1
Gate potential is set by opamp. How do i influence of the pass device OP. how to ensure vdrop=500m vdrop is Iout*rds am i right? if yes so vdrop won't be constant if pass device will work in the linear region, but how to assure working in the saturation?

regards

 

[jwfan]

ldo loop gain

I don't know exactly what you mean. But the Vdrop = Vin - Vout. So if the pass device work in saturation, the output of the OpAmp should not below than Vout-Vth.

 

[huojinsi]

accurate way to do ac analysis of op amp

For LDO circuit, it needs a external capacitor to compensate the loop. Because the out capacitor and load will produce a pole(Fpload=1/(2ΠRloadCout)), the closed loop will be instability under the condition of different Rload. But the ESR of out capacitor will introduce a zero(Fz=1/(2ΠResrCout)) to stabilize the loop,Do u consider this zero?
I think the load is not too light, or else the bias of circuit probably doesn't operate at the normal region.

Hope it help u! Pls correct me if i am wrong!