Ldmos Amplifier Stability Issues

[adnan012]

hi,

I want to know the steps involved stabilizing the ldmos based amplifiers.

I am using MRFE6S9125NR1. Somehow i was able to get 50 to 70 watts from 925 to 960MHz. But there is some stability issue in 880 to 915 band.

ADS LSSP Simulation shows that that amplifiers becomes unstable at 33dbm input power. The amplifier is also unstable at some lower frequencies say 300MHz etc.

I am using the test circuit given in amplifier datasheet but with fr4.

I follow the following steps.

1) DC Bias simulation.
2)Large scale s-parameter LSSP simulation with amplifier terminated to 50 ohm on both input and output sides to estimate the amplifier input and output impedance.
3)Make amplifier stable by adding RLC circuit on gate side.
4) Load pull test of stable amplifier (including RLC circuit from step3 ) to find the optimum load.

5) Input and output matching network design.

6) Harmonic balance simulation.


Some times i noticed that the stability is affected by matching network
and input power level.

Kindly correct me if i am missing some thing.

Regards

 

[albbg]

Since you are using FR4 (eps=4.7) instead of CuClad 250GX (EPS=2.55) did you rescale correctly the substrate thickness and/or the traces width ? I think you can try to simulate the circuit exactly as reported in the datasheet (same substrate, same microstrips) and see if there are stability issues.
You can try to stablilize the transistor by means of a resistive feedback from drain to gate (place a series capacitor just as a DC block). This will increases the noise figure (depending on how feedback you need to provide) but stability and also matching will be improved.

However the power level can affect the stability since the impedance of the transistor is not constant over amplitude.