lcd interfacing with cpld

[r.k.bishoyee]

Hello All,
I am a newbee to xilinx and vhdl.
I want to design a digial clock on my cpld board which will be interfaced with lcd.
I am unable to interface lcd with my cpld(xc9572xl).
Will anybody help me please ???
Thank you in advance

 

[alexan_e]

I don't think it is possible to fit the code needed to drive the lcd with variable text in a 72 macrocell cpld,
It you change it to 7segment displays then the clock and led code will probably fit fine.

For lcd you have to use a cpld with more macrocells and when it comes to more in low price the Altera MAX II has some nice cpld's with many macrocells.
MAX II CPLD Family Overview

If you want to stay with Xilinx then XC95288 has the highest macrocell count in the XC95xx device series, it has 288 macrocells, depending on the lcd code it can probably fit your code.

Alex

 

[mrflibble]

If you want to stay with coolrunner you might need a bigger device than 77 macrocells. For a 256 macrocell device you could try using a picoblaze implementation of a lcd driver in your cpld.

For the picoblaze for cpld see:

PicoBlaze User Resources

And for the lcd driver code for the picoblaze, see:

**broken link removed**

I know these are designs meant for a spartan-3e device, but picoblaze code is picoblaze code. Grab one of the designs that has LCD as "Features Used". That should give you some picoblaze code to get you started with your lcd controller.

Hope that helps.

 

[alexan_e]

The picoblaze in the links in intended for virtexII or coolrunner CPLD's and the core code alone uses more that the available macrocells in a XC9572,
datasheets say 84 VirtexII slices.

Alex

 

[mrflibble]

The picoblaze in the links in intended for virtexII or coolrunner CPLD's and the core code alone uses more that the available macrocells in a XC9572,
datasheets say 84 VirtexII slices.

Alex

I thought he was using coolrunner, but I see I misread. My bad, thanks for clarifying. (and I did say he might need more than 77 macrocells ;-) )

 

[Sudarsan_EDA]

Verilog code for LCD Display Which is Working Good. I found it in Forum.
For more you can find the following links.

https://www.edaboard.com/threads/112086/

https://www.edaboard.com/threads/82432/

// synthesis attribute STEPPING top "ES"
module top (clk, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
parameter n = 27;
parameter k = 17;
(* LOC="AE14" *) input clk; // synthesis attribute PERIOD clk "100.0 MHz"
reg [n-1:0] count=0;
reg lcd_busy=1; // Lumex LCM-S01602DTR/B
reg lcd_stb;
reg [5:0] lcd_code;
reg [6:0] lcd_stuff;
(* LOC="AC17" *) output reg lcd_rs;
(* LOC="AB17" *) output reg lcd_rw;
(* LOC="AF12" *) output reg lcd_7;
(* LOC="AE12" *) output reg lcd_6;
(* LOC="AC10" *) output reg lcd_5;
(* LOC="AB10" *) output reg lcd_4;
(* LOC="AE13" *) output reg lcd_e;

always @ (posedge clk) begin
count <= count + 1;
case (count[k+7:k+2])
0: lcd_code <= 6'b000010; // function set
1: lcd_code <= 6'b000010;
2: lcd_code <= 6'b001100;
3: lcd_code <= 6'b000000; // display on/off control
4: lcd_code <= 6'b001100;
5: lcd_code <= 6'b000000; // display clear
6: lcd_code <= 6'b000001;
7: lcd_code <= 6'b000000; // entry mode set
8: lcd_code <= 6'b000110;
9: lcd_code <= 6'h24; // H
10: lcd_code <= 6'h28;
11: lcd_code <= 6'h26; // e
12: lcd_code <= 6'h25;
13: lcd_code <= 6'h26; // l
14: lcd_code <= 6'h2C;
15: lcd_code <= 6'h26; // l
16: lcd_code <= 6'h2C;
17: lcd_code <= 6'h26; // o
18: lcd_code <= 6'h2F;
19: lcd_code <= 6'h22; //
20: lcd_code <= 6'h20;
21: lcd_code <= 6'h25; // W
22: lcd_code <= 6'h27;
23: lcd_code <= 6'h26; // o
24: lcd_code <= 6'h2F;
25: lcd_code <= 6'h27; // r
26: lcd_code <= 6'h22;
27: lcd_code <= 6'h26; // l
28: lcd_code <= 6'h2C;
29: lcd_code <= 6'h26; // d
30: lcd_code <= 6'h24;
31: lcd_code <= 6'h22; // !
32: lcd_code <= 6'h21;
default: lcd_code <= 6'b010000;
endcase
if (lcd_rw)
lcd_busy <= 0;
lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
end
endmodule