Guest144
Newbie
Hi, I'm fairly new to VHDL and I'm currently testing to write a letter to an LCD display, however I've had no luck. The measured signals are correct but nothing is being displayed, any idea where I might be going wrong. Any advice is appreciated, the FPGA I'm using is the Nexys A7.
Code:
--================================================================
-- LCD state machine controlling the DisplayTech 162B controller
--================================================================
Library IEEE;
use ieee.std_logic_1164.all;
entity LCD_test is
generic(
clk_e : integer := 100e6/1000 --- Amount of bits for the enable signal
);
port(
CLK100MHZ, reset : in std_logic;
RS,RW : out std_logic; -- RS: register select RW: Register Write
E : buffer std_logic; -- Enable signal for the LCD
data : out std_logic_vector(7 downto 0) -- Data sent to the LCD
);
end entity;
architecture arch of LCD_test is
type state is (functionset1, functionset2,functionset3,functionset4, display_off, clear, entry_mode,display_on, write_data, returnhome);
signal old_state, new_state: state;
begin
RW <= '0'; -- Read: 1, Write: 0
--=================================================
-- Generating a 500Hz enable signal (E)
--=================================================
process(CLK100MHZ,reset)
variable cnt : integer;
begin
if reset = '1' then
cnt := 0;
elsif rising_edge(CLK100MHZ) then
cnt := cnt + 1;
E <= '0';
if cnt = clk_e then
cnt := 0;
E <= '1'; --- Creates a clocksignal
end if; -- Creation of E
end if; -- Reset
end process;
--======================================================
-- State register controlling the transisions
--=====================================================
process(CLK100MHZ, reset)
begin
if reset = '1' then
old_state <= functionset1;
elsif E = '1' then --- Find alternative to rising_edge due to mitigate the risk of asycnhronous designs during synthesis
old_state <= new_state;
end if;
end process;
--==================================================
-- State machine controlling the display
--==================================================
process(old_state)
begin
case old_state is
when functionset1 =>
RS <= '0';
data <= "00111000"; -- 8-bit interface, 1-line, 5x8 Font
new_state <= functionset2;
when functionset2 =>
RS <= '0';
data <= "00111000"; -- 8-bit interface, 1-line, 5x8 Font
new_state <= functionset3;
when functionset3 =>
RS <= '0';
data <= "00111000"; -- 8-bit interface, 1-line, 5x8 Font
new_state <= functionset4;
when functionset4 =>
RS <= '0';
data <= "00111000"; -- 8-bit interface, 1-line, 5x8 Font
new_state <= display_off;
when display_off =>
RS <= '0';
data <= "00001000"; -- Display OFF, Cursor OFF, Blink OFF
new_state <= clear;
when clear =>
RS <= '0';
data <= "00000001"; -- Clear Diplay
new_state <= entry_mode;
when entry_mode =>
RS <= '0';
data <= "00000111"; -- Increment and shift the display to the right
new_state <= display_on;
when display_on =>
RS <= '0';
data <= "00001100"; -- Display ON, Cursor OFF, Blink OFF
new_state <= write_data;
when write_data =>
RS <= '0';
data <= "10000101"; -- Letter X
new_state <= returnhome;
when returnhome =>
RS <= '0';
data <= "10000000";-- Returns to display again
new_state <= write_data;
end case;
end process;
end arch;
