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layout questions of custom design block

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aaronwu

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In our chip there are some blocks in critical timing path, which are custom designed. Because full chip will go with ASIC flow, so full chip layout will be done with PR. Any one can help provide some guideline for the custom layout of these blocks? To integrate these blocks layout to PR, I need to know what I should pay attention to during these block layout design.
 

The first steps in laying out the block would be the floorplan of the analog blocks
1) Plan out the point at which you want the signals of the custom block to come out to(ex:left ,right ,top bottom)....which in turn will decide the internal floorplan of the block.
Also dont forget to plan out CLEARLY the way you will give power to the custom block.Unless this is finalised please dont go forward.
2)There are some rules in terms of PR which should be followed(Ex:pins should be on the boundary in a rect and a pin label on it)
3) the will come the internal placement in the block depending on the top level floorplan of the chip as decided above.
Do let me know if you have any specific questions.
 

Thanks, Kapilsn.
Below rules are for standard cell layout, but I don't know whether they also apply to our custom blocks layout?
1. Height of full custom block should be integer multiples of horizontal routing grid defined in standard cell library.
2. Width of full custom block should be integer multiples of vertical routing grid defined in standard cell library.
3. Pins location should be at grid intersections (horizontal and vertical grid intersections).
 

Well I have not followed any such rules for my custom analog blocks which were to be placed in a chip.
 

aaronwu said:
... rules are for standard cell layout, but I don't know whether they also apply to our custom blocks layout?
If your analog blocks are to be used in a standard ASIC PR flow, they must follow these rules. If you don't care for, the PR guys will have to make up for this.
 

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