jimiblues
Newbie level 5
I am currently doing a project using tsmc 65nm technology, where I found some problem in the layout design:
1. when I used the self-generated layout for the transistor, I found different extraction results when the layout is put in different orientations, vertically or horizontally. This gives me a very different result when simulating the fmax. Has any one met the same problem? or can some one explain it?
2. I want to modify the layout of tsmc's rf transistor layout to optimize the fmax, but I wonder that kind of changes are allowed without changing the intrinsic transistor's behaviour and still having a proper simulation? And if I modified the layout, could is still be matched to the transistor in schematic and LVS clean?
I am starter, and I know I am using a very advanced technology, so hope some one could help me on this.
Thanks in advance.
1. when I used the self-generated layout for the transistor, I found different extraction results when the layout is put in different orientations, vertically or horizontally. This gives me a very different result when simulating the fmax. Has any one met the same problem? or can some one explain it?
2. I want to modify the layout of tsmc's rf transistor layout to optimize the fmax, but I wonder that kind of changes are allowed without changing the intrinsic transistor's behaviour and still having a proper simulation? And if I modified the layout, could is still be matched to the transistor in schematic and LVS clean?
I am starter, and I know I am using a very advanced technology, so hope some one could help me on this.
Thanks in advance.