Layout of NMOS-transistors in series

[hannover90]

Hi all,

i do layout of 3 NMOS transistors (in 65 nm technology, tsmc), which are connected in series.
The bulk of each transistor should be connected to the source of the according transistor.

How can I isolate each transistor?

Is it right, if I use Deep-Nmos transistors, which are enclosed by a NWell-rings?

Thanks for any help,

hannover90

 

[Usama Siddiqui]

yes you can use deep nwell transistors, connect the 5th terminal to VDD that will reverse bias the junction and there would be no such leakage as well.

 

[Blue Hawk]

Hi all,

i do layout of 3 NMOS transistors (in 65 nm technology, tsmc), which are connected in series.
The bulk of each transistor should be connected to the source of the according transistor.

How can I isolate each transistor?

Is it right, if I use Deep-Nmos transistors, which are enclosed by a NWell-rings?

Thanks for any help,

hannover90

Yes, you're right..
In order to isolate 3 transistors with bulk connected to corresponding sources, you've to enclose each transistor with NWell guardring.. Only by doing that, you can able to seperate the 4th terminal (bulk)..
You'll get LVS error only by doing above thing,..
You've to draw an psub2 layer over the NWell (bulk) to avoid stamp error while runnig LVS.. --> for this thing, you no need to enclose it by NWell ring..
I think psub2 layer is available in tsmc..

 

[hannover90]

Yes, you're right..
In order to isolate 3 transistors with bulk connected to corresponding sources, you've to enclose each transistor with NWell guardring.. Only by doing that, you can able to seperate the 4th terminal (bulk)..
You'll get LVS error only by doing above thing,..
You've to draw an psub2 layer over the NWell (bulk) to avoid stamp error while runnig LVS.. --> for this thing, you no need to enclose it by NWell ring..
I think psub2 layer is available in tsmc..

Thanks for your reply. Psub2 is helpful for LVS (computer), but it can not be used on the chip. There is no Psub2 in praxis.

 

[erikl]

Psub2 is helpful for LVS (computer), but it can not be used on the chip. There is no Psub2 in praxis.

Of course there's a P+ tap in the P-Well of an isolated NMOS transistor, but it's usually connected to the source of the NMOS, see this image:

 

[Blue Hawk]

Thanks for your reply. Psub2 is helpful for LVS (computer), but it can not be used on the chip. There is no Psub2 in praxis.

Yes, I agree that psub2 layer is a virtual layer..
I'll explain it in some 2 conditions,

1.
Different Grounds--> ex, vssd & vssa :
You'll have different grounds only in your block levels as vssa & vssd.. In that time you'll use psub2 layer to clear your LVS. But In the topmost level (Dphytop or ...) you should connect all your different grounds to one pin ( all substrates'll be connected together ). So there is no need of psub2 layer in future..

2.
In your case ( nmos series conn.. ), you should use psub2 layer to clear LVS..
And there'll be no any problem in future..

I'm not sure with my 2nd point, Please someone make us clear...

Thanks in advance.