Layout of a very long transistor

[analog_ambi]

Hi,
I have a transistor of very long length! w/l=1u/40u. How do I layout? As a single block or as a series of small transistors.

Some say series is good as it will match the models well
Some say at low currents there can be noise injection in the middle transistors in series connection.

My current level is in nanoamps. So i m confused. How do low power circuit designers do such layout?

 

[erikl]

... Some say series is good as it will match the models well

I think you picked the right point. But if you don't need high accuracy results from the analysis, a single long transistor will work quite well -- if it's allowed by your PDK simulation models.

There should be no difference in noise injection for both methods, as long as you use a single common bulk node. Serial transistors with their own bulk nodes (S=B, each in its own well) would possibly catch more noise.