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Layout issue with Digital STD Cell in cadence Virtuoso

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wandola

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Hi everyone. I have designed a small digital block with verilog.

Then I did the synthesis with synopsis DC.

After that I generated the layout in Cadence SoC encounter with the STD cell lib provided by the foundry.

Next I export the encounter layout into a GDS file. I want to import my GDS into cadence virtuoso layout editor to check DRC and LVS. Later I will combine the digital layout with my analog layout.

I have some problems when import my GDS file into cadence virtuoso.

Below are the two screen shots i captured.



The firsts one is the layout in cadence SoC Encounter. The 2nd one is the thing I got after importing my GDS into cadence virtuoso. I basically got nothing. there is no metal layers...

Can anyone help me with this.??

I did first import my STD cell GDS into the cadence virtuoso. After that I important my GDS file. But it is not correct.

Please help..... Im desperate now...
 

dhaval4987

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Try pressing Ctrl+F (Or Shift+F).

If it doesnt work, try pressing Ctrl+X (Or Shift+X).

Lemme know if it worked or not.

Long back, I used some readymade stdcells instead of custom layouts and it just showed the pin connection. One of these served purpose I guess. I dont remember exactly, though so I am not sure now. in this case also it seems only pins.

But try that if it works or not.
 

wandola

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Hey my friend, I have tried Ctrl+F/shfit+F. It doesn't solve the problem. When I press shfit+F, everything in the 2nd pic is gone. the screen is just black. when i press ctrl+F, it comes back to pic 2.

And the red boxes in pic2 are not the pinns. They are the boxes for vias and STD cells I have used...

thanks for help....


still waiting for help...
 

erikl

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Just guessing:
  • For Stream In , did you attach your Technology Library?
  • streamIn LayerMap added?
  • Did you click <Shift> F ?
See these pages from a tutorial: View attachment streamIn.pdf
 

dgnani

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for being a Cadence native tool, Encounter has some pretty annoying features:
- the default map used to streamout has usually nothing to do with the map in the CDBA database. So you probably need a streamin map.
- I have never dealt with it directly in IC5 but I recall those-who-did had to make a separate techlibrary containing all vias, not sure that was strictly necessary or a clumsy way there
- You need to add you cadence library containing std cells as a reference library so they will not be reimported in the design library
- if your streamin of the std cell worked at least you know streamin is working in your version of cadence
- if you have a chance move to IC6, much better
- you might be better off posting this in the digital ic design section
 

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